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ed788b6283
ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181801 91177308-0d34-0410-b5e6-96231b3b80d8
31 lines
1.1 KiB
LLVM
31 lines
1.1 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=LONG %s
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=NORM %s
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define void @myadd(float* %sum, float* %addend) nounwind {
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entry:
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%sum.addr = alloca float*, align 4
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%addend.addr = alloca float*, align 4
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store float* %sum, float** %sum.addr, align 4
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store float* %addend, float** %addend.addr, align 4
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%tmp = load float** %sum.addr, align 4
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%tmp1 = load float* %tmp
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%tmp2 = load float** %addend.addr, align 4
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%tmp3 = load float* %tmp2
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%add = fadd float %tmp1, %tmp3
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%tmp4 = load float** %sum.addr, align 4
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store float %add, float* %tmp4
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ret void
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}
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define i32 @main(i32 %argc, i8** %argv) nounwind {
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entry:
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%ztot = alloca float, align 4
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%z = alloca float, align 4
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store float 0.000000e+00, float* %ztot, align 4
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store float 1.000000e+00, float* %z, align 4
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; CHECK-LONG: blx r
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; CHECK-NORM: bl {{_?}}myadd
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call void @myadd(float* %ztot, float* %z)
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ret i32 0
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}
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