mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-02 07:11:49 +00:00
24732c3363
Before this patch we relied on the order of phi nodes when we looked for phi nodes of the same type. This could prevent vectorization of cases where there was a phi node of a second type in between phi nodes of some type. This is important for vectorization of an internal graphics kernel. On the test suite + external on x86_64 (and on a run on armv7s) it showed no impact on either performance or compile time. radar://15024459 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192537 91177308-0d34-0410-b5e6-96231b3b80d8 |
||
---|---|---|
.. | ||
ADCE | ||
ArgumentPromotion | ||
BBVectorize | ||
BranchFolding | ||
CodeExtractor | ||
CodeGenPrepare | ||
ConstantMerge | ||
ConstProp | ||
CorrelatedValuePropagation | ||
DeadArgElim | ||
DeadStoreElimination | ||
DebugIR | ||
EarlyCSE | ||
FunctionAttrs | ||
GCOVProfiling | ||
GlobalDCE | ||
GlobalOpt | ||
GVN | ||
IndVarSimplify | ||
Inline | ||
InstCombine | ||
InstSimplify | ||
Internalize | ||
IPConstantProp | ||
JumpThreading | ||
LCSSA | ||
LICM | ||
LoopDeletion | ||
LoopIdiom | ||
LoopRotate | ||
LoopSimplify | ||
LoopStrengthReduce | ||
LoopUnroll | ||
LoopUnswitch | ||
LoopVectorize | ||
LowerAtomic | ||
LowerExpectIntrinsic | ||
LowerInvoke | ||
LowerSwitch | ||
Mem2Reg | ||
MemCpyOpt | ||
MergeFunc | ||
MetaRenamer | ||
ObjCARC | ||
PhaseOrdering | ||
PruneEH | ||
Reassociate | ||
Reg2Mem | ||
ScalarRepl | ||
SCCP | ||
SimplifyCFG | ||
Sink | ||
SLPVectorizer | ||
SROA | ||
StripSymbols | ||
StructurizeCFG | ||
TailCallElim | ||
TailDup |