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https://github.com/c64scene-ar/llvm-6502.git
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375cbe4143
instruction (vmaddfp) to conform with IEEE to ensure the sign of a zero result when resulting product is -0.0. The -0.0 vector addend to vmaddfp is generated by a creating a vector with full bits sets and then shifting each elements by 31-bits to the left, resulting in a vector of 0x80000000 (or -0.0 as float). The 'buildvec_canonicalize.ll' was adjusted to reflect this change and the 'vec_mul.ll' was complemented with the float vector multiplication test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168998 91177308-0d34-0410-b5e6-96231b3b80d8
47 lines
1.5 KiB
LLVM
47 lines
1.5 KiB
LLVM
; RUN: llc < %s -mattr=+altivec | FileCheck %s
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define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
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%tmp = load <4 x i32>* %X ; <<4 x i32>> [#uses=1]
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%tmp2 = load <4 x i32>* %Y ; <<4 x i32>> [#uses=1]
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%tmp3 = mul <4 x i32> %tmp, %tmp2 ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %tmp3
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}
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; CHECK: test_v4i32:
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; CHECK: vmsumuhm
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; CHECK-NOT: mullw
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define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) {
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%tmp = load <8 x i16>* %X ; <<8 x i16>> [#uses=1]
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%tmp2 = load <8 x i16>* %Y ; <<8 x i16>> [#uses=1]
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%tmp3 = mul <8 x i16> %tmp, %tmp2 ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %tmp3
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}
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; CHECK: test_v8i16:
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; CHECK: vmladduhm
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; CHECK-NOT: mullw
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define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) {
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%tmp = load <16 x i8>* %X ; <<16 x i8>> [#uses=1]
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%tmp2 = load <16 x i8>* %Y ; <<16 x i8>> [#uses=1]
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%tmp3 = mul <16 x i8> %tmp, %tmp2 ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp3
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}
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; CHECK: test_v16i8:
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; CHECK: vmuloub
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; CHECK: vmuleub
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; CHECK-NOT: mullw
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define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) {
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%tmp = load <4 x float>* %X
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%tmp2 = load <4 x float>* %Y
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%tmp3 = fmul <4 x float> %tmp, %tmp2
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ret <4 x float> %tmp3
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}
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; Check the creation of a negative zero float vector by creating a vector of
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; all bits set and shifting it 31 bits to left, resulting a an vector of
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; 4 x 0x80000000 (-0.0 as float).
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; CHECK: test_float:
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; CHECK: vspltisw [[ZNEG:[0-9]+]], -1
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; CHECK: vslw {{[0-9]+}}, [[ZNEG]], [[ZNEG]]
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; CHECK: vmaddfp
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