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https://github.com/c64scene-ar/llvm-6502.git
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db3a9e64f8
The work on this project was left in an unfinished and inconsistent state. Hopefully someone will eventually get a chance to implement this feature, but in the meantime, it is better to put things back the way the were. I have left support in the bitcode reader to handle the case-range bitcode format, so that we do not lose bitcode compatibility with the llvm 3.3 release. This reverts the following commits: 155464, 156374, 156377, 156613, 156704, 156757, 156804 156808, 156985, 157046, 157112, 157183, 157315, 157384, 157575, 157576, 157586, 157612, 157810, 157814, 157815, 157880, 157881, 157882, 157884, 157887, 157901, 158979, 157987, 157989, 158986, 158997, 159076, 159101, 159100, 159200, 159201, 159207, 159527, 159532, 159540, 159583, 159618, 159658, 159659, 159660, 159661, 159703, 159704, 160076, 167356, 172025, 186736 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190328 91177308-0d34-0410-b5e6-96231b3b80d8
68 lines
1.3 KiB
LLVM
68 lines
1.3 KiB
LLVM
; RUN: llvm-dis < %s.bc| FileCheck %s
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; case-ranges.ll.bc was generated by passing this file to llvm-as from the 3.3
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; release of LLVM. This tests that the bitcode for switches from that release
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; can still be read.
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define i32 @foo(i32 %x) nounwind ssp uwtable {
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; CHECK: define i32 @foo
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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store i32 %x, i32* %2, align 4
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%3 = load i32* %2, align 4
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switch i32 %3, label %9 [
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; CHECK: switch i32 %3, label %9
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i32 -3, label %4
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; CHECK-NEXT: i32 -3, label %4
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i32 -2, label %4
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; CHECK-NEXT: i32 -2, label %4
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i32 -1, label %4
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; CHECK-NEXT: i32 -1, label %4
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i32 0, label %4
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; CHECK-NEXT: i32 0, label %4
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i32 1, label %4
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; CHECK-NEXT: i32 1, label %4
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i32 2, label %4
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; CHECK-NEXT: i32 2, label %4
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i32 4, label %5
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; CHECK-NEXT: i32 4, label %5
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i32 5, label %6
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; CHECK-NEXT: i32 5, label %6
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i32 6, label %7
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; CHECK-NEXT: i32 6, label %7
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i32 7, label %8
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; CHECK-NEXT: i32 7, label %8
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]
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; <label>:4
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store i32 -1, i32* %1
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br label %11
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; <label>:5
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store i32 2, i32* %1
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br label %11
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; <label>:6
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store i32 1, i32* %1
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br label %11
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; <label>:7
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store i32 4, i32* %1
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br label %11
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; <label>:8
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store i32 3, i32* %1
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br label %11
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; <label>:9
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br label %10
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; <label>:10
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store i32 0, i32* %1
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br label %11
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; <label>:11
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%12 = load i32* %1
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ret i32 %12
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}
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