Hal Finkel 3d2ce7a5a7 Swap PPC isel operands to allow for 0-folding ...

The PPC isel instruction can fold 0 into the first operand (thus eliminating
the need to materialize a zero-containing register when the 'true' result of
the isel is 0). When the isel is fed by a bit register operation that we can
invert, do so as part of the bit-register-operation peephole routine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202469 91177308-0d34-0410-b5e6-96231b3b80d8

2014-02-28 06:11:16 +00:00

..

AArch64

AArch64: simplify tbl/tbx polymorphism

2014-02-26 11:55:09 +00:00

ARM

Debug info: Remove ARMAsmPrinter::EmitDwarfRegOp(). AsmPrinter can now

2014-02-27 17:56:08 +00:00

CPP

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Generic

Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call

2014-02-13 14:44:26 +00:00

Hexagon

Fix broken CHECK lines

2014-02-16 07:31:05 +00:00

Inputs

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Mips

[mips] Make it impossible to have UnknownABI in CodeGen and Integrated Assembler.

2014-02-20 14:58:19 +00:00

MSP430

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NVPTX

[NVPTX] Fix emitting aggregate parameters

2014-01-28 18:35:29 +00:00

PowerPC

Swap PPC isel operands to allow for 0-folding

2014-02-28 06:11:16 +00:00

R600

R600/SI: Optimize SI_KILL for constant operands

2014-02-27 01:47:09 +00:00

SPARC

Lower FNEG just like FABS to fneg[ds] and fmov[ds], thus avoiding

2014-02-27 19:26:29 +00:00

SystemZ

Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call

2014-02-13 14:44:26 +00:00

Thumb

Add triples to try to fix the windows bots.

2014-02-13 16:49:47 +00:00

Thumb2

ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block

2014-02-26 11:27:28 +00:00

X86

Stop test/CodeGen/X86/v4i32load-crash.ll targeting non-X86-64 targets.

2014-02-27 09:24:31 +00:00

XCore

[XCore] Support functions returning more than 4 words.

2014-02-27 17:47:54 +00:00