mirror of
https://github.com/c64scene-ar/llvm-6502.git
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785bd59852
Properly constrain the operand register class for instructions used in [sz]ext expansion. Update more tests to use the verifier now that we're getting the register classes correct. rdar://12594152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188594 91177308-0d34-0410-b5e6-96231b3b80d8
79 lines
2.0 KiB
LLVM
79 lines
2.0 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
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define i32 @icmp_i16_signed(i16 %a, i16 %b) nounwind {
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entry:
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; ARM: icmp_i16_signed
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; ARM: sxth r0, r0
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; ARM: sxth r1, r1
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; ARM: cmp r0, r1
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; THUMB: icmp_i16_signed
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; THUMB: sxth r0, r0
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; THUMB: sxth r1, r1
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; THUMB: cmp r0, r1
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%cmp = icmp slt i16 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define i32 @icmp_i16_unsigned(i16 %a, i16 %b) nounwind {
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entry:
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; ARM: icmp_i16_unsigned
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; ARM: uxth r0, r0
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; ARM: uxth r1, r1
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; ARM: cmp r0, r1
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; THUMB: icmp_i16_unsigned
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; THUMB: uxth r0, r0
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; THUMB: uxth r1, r1
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; THUMB: cmp r0, r1
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%cmp = icmp ult i16 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define i32 @icmp_i8_signed(i8 %a, i8 %b) nounwind {
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entry:
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; ARM: icmp_i8_signed
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; ARM: sxtb r0, r0
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; ARM: sxtb r1, r1
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; ARM: cmp r0, r1
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; THUMB: icmp_i8_signed
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; THUMB: sxtb r0, r0
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; THUMB: sxtb r1, r1
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; THUMB: cmp r0, r1
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%cmp = icmp sgt i8 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define i32 @icmp_i8_unsigned(i8 %a, i8 %b) nounwind {
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entry:
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; ARM: icmp_i8_unsigned
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; ARM: and r0, r0, #255
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; ARM: and r1, r1, #255
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; ARM: cmp r0, r1
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; THUMB: icmp_i8_unsigned
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; THUMB: and r0, r0, #255
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; THUMB: and r1, r1, #255
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; THUMB: cmp r0, r1
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%cmp = icmp ugt i8 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define i32 @icmp_i1_unsigned(i1 %a, i1 %b) nounwind {
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entry:
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; ARM: icmp_i1_unsigned
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; ARM: and r0, r0, #1
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; ARM: and r1, r1, #1
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; ARM: cmp r0, r1
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; THUMB: icmp_i1_unsigned
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; THUMB: and r0, r0, #1
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; THUMB: and r1, r1, #1
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; THUMB: cmp r0, r1
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%cmp = icmp ult i1 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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