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c15d3a82ae
These tests mistakenly assume that CHECK is still available even if an explicit prefix is specified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201492 91177308-0d34-0410-b5e6-96231b3b80d8
98 lines
3.9 KiB
LLVM
98 lines
3.9 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=fast -optimize-regalloc=0 | FileCheck %s -check-prefix=A8 -check-prefix=CHECK
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; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-m3 -regalloc=fast -optimize-regalloc=0 | FileCheck %s -check-prefix=M3 -check-prefix=CHECK
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; rdar://6949835
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; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=BASIC -check-prefix=CHECK
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; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=greedy | FileCheck %s -check-prefix=GREEDY -check-prefix=CHECK
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; Magic ARM pair hints works best with linearscan / fast.
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; Cortex-M3 errata 602117: LDRD with base in list may result in incorrect base
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; register when interrupted or faulted.
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@b = external global i64*
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define i64 @t(i64 %a) nounwind readonly {
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entry:
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; A8-LABEL: t:
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; A8: ldrd r2, r3, [r2]
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; M3-LABEL: t:
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; M3-NOT: ldrd
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%0 = load i64** @b, align 4
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%1 = load i64* %0, align 4
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%2 = mul i64 %1, %a
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ret i64 %2
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}
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; rdar://10435045 mixed LDRi8/LDRi12
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;
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; In this case, LSR generate a sequence of LDRi8/LDRi12. We should be
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; able to generate an LDRD pair here, but this is highly sensitive to
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; regalloc hinting. So, this doubles as a register allocation
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; test. RABasic currently does a better job within the inner loop
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; because of its *lack* of hinting ability. Whereas RAGreedy keeps
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; R0/R1/R2 live as the three arguments, forcing the LDRD's odd
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; destination into R3. We then sensibly split LDRD again rather then
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; evict another live range or use callee saved regs. Sorry if the test
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; is sensitive to Regalloc changes, but it is an interesting case.
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;
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; BASIC: @f
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; BASIC: %bb
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; BASIC: ldrd
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; BASIC: str
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; GREEDY: @f
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; GREEDY: %bb
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; GREEDY: ldrd
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; GREEDY: str
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define void @f(i32* nocapture %a, i32* nocapture %b, i32 %n) nounwind {
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entry:
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%0 = add nsw i32 %n, -1 ; <i32> [#uses=2]
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%1 = icmp sgt i32 %0, 0 ; <i1> [#uses=1]
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br i1 %1, label %bb, label %return
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bb: ; preds = %bb, %entry
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%i.03 = phi i32 [ %tmp, %bb ], [ 0, %entry ] ; <i32> [#uses=3]
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%scevgep = getelementptr i32* %a, i32 %i.03 ; <i32*> [#uses=1]
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%scevgep4 = getelementptr i32* %b, i32 %i.03 ; <i32*> [#uses=1]
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%tmp = add i32 %i.03, 1 ; <i32> [#uses=3]
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%scevgep5 = getelementptr i32* %a, i32 %tmp ; <i32*> [#uses=1]
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%2 = load i32* %scevgep, align 4 ; <i32> [#uses=1]
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%3 = load i32* %scevgep5, align 4 ; <i32> [#uses=1]
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%4 = add nsw i32 %3, %2 ; <i32> [#uses=1]
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store i32 %4, i32* %scevgep4, align 4
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%exitcond = icmp eq i32 %tmp, %0 ; <i1> [#uses=1]
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br i1 %exitcond, label %return, label %bb
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return: ; preds = %bb, %entry
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ret void
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}
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; rdar://13978317
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; Pair of loads not formed when lifetime markers are set.
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%struct.Test = type { i32, i32, i32 }
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@TestVar = external global %struct.Test
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define void @Func1() nounwind ssp {
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; CHECK: @Func1
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entry:
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; A8: movw [[BASE:r[0-9]+]], :lower16:{{.*}}TestVar{{.*}}
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; A8: movt [[BASE]], :upper16:{{.*}}TestVar{{.*}}
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; A8: ldrd [[FIELD1:r[0-9]+]], [[FIELD2:r[0-9]+]], {{\[}}[[BASE]], #4]
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; A8-NEXT: add [[FIELD1]], [[FIELD2]]
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; A8-NEXT: str [[FIELD1]], {{\[}}[[BASE]]{{\]}}
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%orig_blocks = alloca [256 x i16], align 2
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%0 = bitcast [256 x i16]* %orig_blocks to i8*call void @llvm.lifetime.start(i64 512, i8* %0) nounwind
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%tmp1 = load i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 1), align 4
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%tmp2 = load i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 2), align 4
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%add = add nsw i32 %tmp2, %tmp1
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store i32 %add, i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 0), align 4
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call void @llvm.lifetime.end(i64 512, i8* %0) nounwind
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ret void
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}
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declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind
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declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind
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