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https://github.com/c64scene-ar/llvm-6502.git
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645efd763d
This should fix the ARM bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197555 91177308-0d34-0410-b5e6-96231b3b80d8
60 lines
1.9 KiB
LLVM
60 lines
1.9 KiB
LLVM
; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
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; RUN: llc < %s -march=arm -float-abi=soft -mcpu=swift | FileCheck %s --check-prefix=SWIFT
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; CHECK: t1
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; CHECK: vld1.64
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; CHECK: vld1.64
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; CHECK: vadd.i64 q
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; CHECK: vst1.64
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; SWIFT: t1
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; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
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; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
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; SWIFT: vadd.i64 q
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; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
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define void @t1(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind {
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entry:
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%0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1]
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%1 = load <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1]
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%2 = add <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1]
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%3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
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store <4 x i32> %3, <4 x i32>* %r, align 16
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ret void
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}
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; CHECK: t2
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; CHECK: vld1.64
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; CHECK: vld1.64
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; CHECK: vsub.i64 q
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; CHECK: vmov r0, r1, d
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; CHECK: vmov r2, r3, d
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; SWIFT: t2
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; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
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; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
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; SWIFT: vsub.i64 q
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; SWIFT: vmov r0, r1, d
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; SWIFT: vmov r2, r3, d
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define <4 x i32> @t2(<2 x i64>* %a, <2 x i64>* %b) nounwind readonly {
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entry:
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%0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1]
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%1 = load <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1]
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%2 = sub <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1]
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%3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %3
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}
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; Limited alignment.
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; SWIFT: t3
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; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}}
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; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}}
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; SWIFT: vadd.i64 q
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; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}}
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define void @t3(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind {
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entry:
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%0 = load <2 x i64>* %a, align 8
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%1 = load <2 x i64>* %b, align 8
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%2 = add <2 x i64> %0, %1
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%3 = bitcast <2 x i64> %2 to <4 x i32>
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store <4 x i32> %3, <4 x i32>* %r, align 8
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ret void
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}
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