mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-10-31 08:16:47 +00:00
66742f023c
Summary: This commit gives an address mode to the PLD instruction. We were getting an assertion failure in the frame lowering code because we had code that was doing a pld of a stack allocated address. The frame lowering was checking the address mode and then asserting because pld had none defined. This commit fixes pld for arm mode. There was a previous fix for thumb mode in a separate commit. The commit for thumb mode added a test in a separate file because it would otherwise fail for arm. This commit moves the thumb test back into the prefetch.ll file and adds the corresponding arm test. Differential Revision: http://llvm-reviews.chandlerc.com/D2622 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200248 91177308-0d34-0410-b5e6-96231b3b80d8
96 lines
2.2 KiB
LLVM
96 lines
2.2 KiB
LLVM
; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld
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; RUN: llc < %s -march=thumb -mattr=+v7 | FileCheck %s -check-prefix=THUMB2
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; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s -check-prefix=ARM
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; RUN: llc < %s -march=arm -mcpu=cortex-a9-mp | FileCheck %s -check-prefix=ARM-MP
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; rdar://8601536
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define void @t1(i8* %ptr) nounwind {
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entry:
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; ARM-LABEL: t1:
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; ARM-NOT: pldw [r0]
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; ARM: pld [r0]
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; ARM-MP-LABEL: t1:
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; ARM-MP: pldw [r0]
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; ARM-MP: pld [r0]
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; THUMB2-LABEL: t1:
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; THUMB2-NOT: pldw [r0]
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; THUMB2: pld [r0]
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tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
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ret void
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}
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define void @t2(i8* %ptr) nounwind {
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entry:
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; ARM-LABEL: t2:
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; ARM: pld [r0, #1023]
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; THUMB2-LABEL: t2:
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; THUMB2: pld [r0, #1023]
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%tmp = getelementptr i8* %ptr, i32 1023
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tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3, i32 1 )
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ret void
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}
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define void @t3(i32 %base, i32 %offset) nounwind {
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entry:
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; ARM-LABEL: t3:
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; ARM: pld [r0, r1, lsr #2]
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; THUMB2-LABEL: t3:
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; THUMB2: lsrs r1, r1, #2
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; THUMB2: pld [r0, r1]
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%tmp1 = lshr i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i8*
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tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3, i32 1 )
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ret void
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}
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define void @t4(i32 %base, i32 %offset) nounwind {
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entry:
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; ARM-LABEL: t4:
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; ARM: pld [r0, r1, lsl #2]
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; THUMB2-LABEL: t4:
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; THUMB2: pld [r0, r1, lsl #2]
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%tmp1 = shl i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i8*
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tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3, i32 1 )
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ret void
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}
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declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
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define void @t5(i8* %ptr) nounwind {
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entry:
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; ARM-LABEL: t5:
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; ARM: pli [r0]
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; THUMB2-LABEL: t5:
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; THUMB2: pli [r0]
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 0 )
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ret void
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}
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define void @t6() {
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entry:
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;ARM-LABEL: t6:
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;ARM: pld [sp]
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;ARM: pld [sp, #50]
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;THUMB2-LABEL: t6:
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;THUMB2: pld [sp]
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;THUMB2: pld [sp, #50]
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%red = alloca [100 x i8], align 1
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%0 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 0
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%1 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 50
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call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 1)
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call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1)
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ret void
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}
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