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https://github.com/c64scene-ar/llvm-6502.git
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71313f88cb
Similarly to the vshrn instructions, these are simple zext/sext + trunc operations. Using normal LLVM IR should allow for better code, and more sharing with the AArch64 backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201093 91177308-0d34-0410-b5e6-96231b3b80d8
117 lines
3.7 KiB
LLVM
117 lines
3.7 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vshlls8:
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;CHECK: vshll.s8
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%tmp1 = load <8 x i8>* %A
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%sext = sext <8 x i8> %tmp1 to <8 x i16>
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%shift = shl <8 x i16> %sext, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <8 x i16> %shift
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}
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define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: vshlls16:
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;CHECK: vshll.s16
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%tmp1 = load <4 x i16>* %A
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%sext = sext <4 x i16> %tmp1 to <4 x i32>
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%shift = shl <4 x i32> %sext, <i32 15, i32 15, i32 15, i32 15>
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ret <4 x i32> %shift
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}
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define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vshlls32:
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;CHECK: vshll.s32
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%tmp1 = load <2 x i32>* %A
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%sext = sext <2 x i32> %tmp1 to <2 x i64>
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%shift = shl <2 x i64> %sext, <i64 31, i64 31>
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ret <2 x i64> %shift
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}
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define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vshllu8:
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;CHECK: vshll.u8
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%tmp1 = load <8 x i8>* %A
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%zext = zext <8 x i8> %tmp1 to <8 x i16>
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%shift = shl <8 x i16> %zext, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <8 x i16> %shift
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}
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define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: vshllu16:
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;CHECK: vshll.u16
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%tmp1 = load <4 x i16>* %A
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%zext = zext <4 x i16> %tmp1 to <4 x i32>
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%shift = shl <4 x i32> %zext, <i32 15, i32 15, i32 15, i32 15>
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ret <4 x i32> %shift
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}
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define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vshllu32:
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;CHECK: vshll.u32
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%tmp1 = load <2 x i32>* %A
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%zext = zext <2 x i32> %tmp1 to <2 x i64>
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%shift = shl <2 x i64> %zext, <i64 31, i64 31>
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ret <2 x i64> %shift
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}
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; The following tests use the maximum shift count, so the signedness is
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; irrelevant. Test both signed and unsigned versions.
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define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vshlli8:
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;CHECK: vshll.i8
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%tmp1 = load <8 x i8>* %A
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%sext = sext <8 x i8> %tmp1 to <8 x i16>
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%shift = shl <8 x i16> %sext, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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ret <8 x i16> %shift
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}
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define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: vshlli16:
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;CHECK: vshll.i16
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%tmp1 = load <4 x i16>* %A
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%zext = zext <4 x i16> %tmp1 to <4 x i32>
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%shift = shl <4 x i32> %zext, <i32 16, i32 16, i32 16, i32 16>
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ret <4 x i32> %shift
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}
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define <2 x i64> @vshlli32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vshlli32:
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;CHECK: vshll.i32
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%tmp1 = load <2 x i32>* %A
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%zext = zext <2 x i32> %tmp1 to <2 x i64>
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%shift = shl <2 x i64> %zext, <i64 32, i64 32>
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ret <2 x i64> %shift
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}
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; And these have a shift just out of range so separate vmovl and vshl
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; instructions are needed.
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define <8 x i16> @vshllu8_bad(<8 x i8>* %A) nounwind {
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; CHECK-LABEL: vshllu8_bad:
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; CHECK: vmovl.u8
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; CHECK: vshl.i16
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%tmp1 = load <8 x i8>* %A
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%zext = zext <8 x i8> %tmp1 to <8 x i16>
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%shift = shl <8 x i16> %zext, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
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ret <8 x i16> %shift
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}
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define <4 x i32> @vshlls16_bad(<4 x i16>* %A) nounwind {
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; CHECK-LABEL: vshlls16_bad:
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; CHECK: vmovl.s16
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; CHECK: vshl.i32
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%tmp1 = load <4 x i16>* %A
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%sext = sext <4 x i16> %tmp1 to <4 x i32>
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%shift = shl <4 x i32> %sext, <i32 17, i32 17, i32 17, i32 17>
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ret <4 x i32> %shift
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}
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define <2 x i64> @vshllu32_bad(<2 x i32>* %A) nounwind {
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; CHECK-LABEL: vshllu32_bad:
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; CHECK: vmovl.u32
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; CHECK: vshl.i64
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%tmp1 = load <2 x i32>* %A
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%zext = zext <2 x i32> %tmp1 to <2 x i64>
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%shift = shl <2 x i64> %zext, <i64 33, i64 33>
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ret <2 x i64> %shift
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}
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