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e6c56433de
ELF ABI. A varargs parameter consisting of a single-precision floating-point value, or of a single-element aggregate containing a single-precision floating-point value, must be passed in the low-order (rightmost) four bytes of the doubleword stack slot reserved for that parameter. If there are GPR protocol registers remaining, the parameter must also be mirrored in the low-order four bytes of the reserved GPR. Prior to this patch, such parameters were being passed in the high-order four bytes of the stack slot and the mirrored GPR. The patch adds a new test case to verify the correct code generation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166968 91177308-0d34-0410-b5e6-96231b3b80d8
24 lines
740 B
LLVM
24 lines
740 B
LLVM
; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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%struct.Sf1 = type { float }
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define void @foo(float inreg %s.coerce) nounwind {
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entry:
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%s = alloca %struct.Sf1, align 4
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%coerce.dive = getelementptr %struct.Sf1* %s, i32 0, i32 0
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store float %s.coerce, float* %coerce.dive, align 1
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%coerce.dive1 = getelementptr %struct.Sf1* %s, i32 0, i32 0
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%0 = load float* %coerce.dive1, align 1
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call void (i32, ...)* @testvaSf1(i32 1, float inreg %0)
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ret void
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}
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; CHECK: stfs {{[0-9]+}}, 60(1)
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; CHECK: ld 4, 56(1)
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; CHECK: bl
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declare void @testvaSf1(i32, ...)
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