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One unusual feature of the z architecture is that the result of a previous load can be reused indefinitely for subsequent loads, even if a cache-coherent store to that location is performed by another CPU. A special serializing instruction must be used if you want to force a load to be reattempted. Since volatile loads are not supposed to be omitted in this way, we should insert a serializing instruction before each such load. The same goes for atomic loads. The patch implements this at the IR->DAG boundary, in a similar way to atomic fences. It is a no-op for targets other than SystemZ. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196905 91177308-0d34-0410-b5e6-96231b3b80d8
22 lines
576 B
LLVM
22 lines
576 B
LLVM
; Test serialization instructions.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | \
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; RUN: FileCheck %s -check-prefix=CHECK-FULL
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | \
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; RUN: FileCheck %s -check-prefix=CHECK-FAST
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; Check that volatile loads produce a serialisation.
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define i32 @f1(i32 *%src) {
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; CHECK-FULL-LABEL: f1:
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; CHECK-FULL: bcr 15, %r0
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; CHECK-FULL: l %r2, 0(%r2)
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; CHECK-FULL: br %r14
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;
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; CHECK-FAST-LABEL: f1:
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; CHECK-FAST: bcr 14, %r0
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; CHECK-FAST: l %r2, 0(%r2)
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; CHECK-FAST: br %r14
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%val = load volatile i32 *%src
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ret i32 %val
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}
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