llvm-6502/test/CodeGen/X86/select-with-and-or.ll at 37c04a0d4d0df0e2efddcc76a1036a9fc384e61a

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Michael Liao bf53841cfe Optimize vector select from all 0s or all 1s

As packed comparisons in AVX/SSE produce all 0s or all 1s in each SIMD lane,
vector select could be simplified to AND/OR or removed if one or both values
being selected is all 0s or all 1s.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179267 91177308-0d34-0410-b5e6-96231b3b80d8

2013-04-11 05:15:54 +00:00

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