llvm-6502/test/MC/Disassembler
Craig Topper 6ee83c07a0 Test case for r204305.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204316 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 06:45:10 +00:00
..
AArch64 [AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction. 2013-11-29 01:29:16 +00:00
ARM ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions 2014-01-12 04:36:01 +00:00
Mips This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well. 2014-03-03 13:12:59 +00:00
PowerPC [PowerPC] Initial support for the VSX instruction set 2014-03-13 07:58:58 +00:00
Sparc [Sparc] Add support for decoding 'swap' instruction. 2014-03-09 23:32:07 +00:00
SystemZ [SystemZ] Add MC support for interlocked-access 1 instructions 2013-12-24 15:14:05 +00:00
X86 Test case for r204305. 2014-03-20 06:45:10 +00:00
XCore [tests] Cleanup initialization of test suffixes. 2013-08-16 00:37:11 +00:00