llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-19 20:34:38 +00:00

History

Juergen Ributzka fcfc234130 [X86] Emulate AVX 256bit MIN/MAX support by splitting the vector.

In AVX 256bit vectors are valid vectors and therefore the Type Legalizer doesn't
split the VSELECT and SETCC nodes. AVX only supports MIN/MAX on 128bit vectors
and this fix enables vector splitting for this special case in the X86 DAG
Combiner.

This fix is related to PR16695, PR17002, and <rdar://problem/14594431>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191131 91177308-0d34-0410-b5e6-96231b3b80d8

2013-09-21 04:55:22 +00:00

AArch64

Implement 3 AArch64 neon instructions : umov smov ins.

2013-09-17 02:21:02 +00:00

ARM

Initialize BSSSection explicitly in InitMachOMCObjectFileInfo() to appease msvc.

2013-09-21 02:34:45 +00:00

CPP

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