Tim Northover 4413539ee4 ARM: support legalisation of "fptrunc ... to half" operations. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213373 91177308-0d34-0410-b5e6-96231b3b80d8

2014-07-18 13:01:19 +00:00

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CMakeLists.txt

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DAGCombiner.cpp

Revert "[x86] Fold extract_vector_elt of a load into the Load's address computation."

2014-07-18 00:15:50 +00:00

FastISel.cpp

[FastISel] Local values shouldn't be alive across an inline asm call with side effects.

2014-07-16 22:20:51 +00:00

FunctionLoweringInfo.cpp

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InstrEmitter.cpp

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InstrEmitter.h

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LegalizeDAG.cpp

CodeGen: generate single libcall for fptrunc -> f16 operations.

2014-07-17 11:12:12 +00:00

LegalizeFloatTypes.cpp

ARM: support legalisation of "fptrunc ... to half" operations.

2014-07-18 13:01:19 +00:00

LegalizeIntegerTypes.cpp

CodeGen: extend f16 conversions to permit types > float.

2014-07-17 10:51:23 +00:00

LegalizeTypes.cpp

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LegalizeTypes.h

ARM: support legalisation of "fptrunc ... to half" operations.

2014-07-18 13:01:19 +00:00

LegalizeTypesGeneric.cpp

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LegalizeVectorOps.cpp

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LegalizeVectorTypes.cpp

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LLVMBuild.txt

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Makefile

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ResourcePriorityQueue.cpp

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ScheduleDAGFast.cpp

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ScheduleDAGRRList.cpp

fixed typo

2014-07-14 18:21:07 +00:00

ScheduleDAGSDNodes.cpp

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ScheduleDAGSDNodes.h

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ScheduleDAGVLIW.cpp

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SDNodeDbgValue.h

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SelectionDAG.cpp

AArch64: Constant fold converting vector setcc results to float.

2014-07-18 00:40:52 +00:00

SelectionDAGBuilder.cpp

CodeGen: extend f16 conversions to permit types > float.

2014-07-17 10:51:23 +00:00

SelectionDAGBuilder.h

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SelectionDAGDumper.cpp

CodeGen: extend f16 conversions to permit types > float.

2014-07-17 10:51:23 +00:00

SelectionDAGISel.cpp

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SelectionDAGPrinter.cpp

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TargetLowering.cpp

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TargetSelectionDAGInfo.cpp

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