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3a106a2813
For best-case performance on Cortex-A57, we should try to use a balanced mix of odd and even D-registers when performing a critical sequence of independent, non-quadword FP/ASIMD floating-point multiply or multiply-accumulate operations.
This pass attempts to detect situations where the register allocation may adversely affect this load balancing and to change the registers used so as to better utilize the CPU.
Ideally we'd just take each multiply or multiply-accumulate in turn and allocate it alternating even or odd registers. However, multiply-accumulates are most efficiently performed in the same functional unit as their accumulation operand. Therefore this pass tries to find maximal sequences ("Chains") of multiply-accumulates linked via their accumulation operand, and assign them all the same "color" (oddness/evenness).
This optimization affects S-register and D-register floating point multiplies and FMADD/FMAs, as well as vector (floating point only) muls and FMADD/FMA. Q register instructions (and 128-bit vector instructions) are not affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215199 91177308-0d34-0410-b5e6-96231b3b80d8
51 lines
1.7 KiB
C++
51 lines
1.7 KiB
C++
//==-- AArch64.h - Top-level interface for AArch64 --------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// AArch64 back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef TARGET_AArch64_H
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#define TARGET_AArch64_H
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class AArch64TargetMachine;
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class FunctionPass;
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class MachineFunctionPass;
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FunctionPass *createAArch64DeadRegisterDefinitions();
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FunctionPass *createAArch64ConditionalCompares();
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FunctionPass *createAArch64AdvSIMDScalar();
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FunctionPass *createAArch64BranchRelaxation();
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FunctionPass *createAArch64ISelDag(AArch64TargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createAArch64StorePairSuppressPass();
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FunctionPass *createAArch64ExpandPseudoPass();
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FunctionPass *createAArch64LoadStoreOptimizationPass();
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ModulePass *createAArch64PromoteConstantPass();
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FunctionPass *createAArch64AddressTypePromotionPass();
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FunctionPass *createAArch64A57FPLoadBalancing();
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/// \brief Creates an ARM-specific Target Transformation Info pass.
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ImmutablePass *
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createAArch64TargetTransformInfoPass(const AArch64TargetMachine *TM);
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FunctionPass *createAArch64CleanupLocalDynamicTLSPass();
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FunctionPass *createAArch64CollectLOHPass();
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} // end namespace llvm
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#endif
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