Samuel Antao 3a660c933a Add assertion to detect invalid registers in the PowerPC MC instruction lowering.
We have observed that noreg was being generated due to a bug in FastIsel and was not being detected during emission. It happens that in the Asm emission there is an assertion that detects this in getRegisterName() from the tbl-generated file PPCGenAsmWriter.inc. However, when emitting an Obj file, invalid registers can be emitted given that no check are made in getBinaryCodeFromInstr() from PPCGenMCCodeEmitter.inc. In order to cover all cases this adds an assertion for reg operands in LowerPPCMachineInstrToMCInst.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232525 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-17 19:31:19 +00:00
2015-03-17 19:26:23 +00:00
2014-04-07 03:57:04 +00:00
2014-03-02 13:08:46 +00:00
2015-01-30 21:59:28 +00:00
2015-03-12 01:25:29 +00:00
2015-02-04 18:46:00 +00:00

Low Level Virtual Machine (LLVM)
================================

This directory and its subdirectories contain source code for LLVM,
a toolkit for the construction of highly optimized compilers,
optimizers, and runtime environments.

LLVM is open source software. You may freely distribute it under the terms of
the license agreement found in LICENSE.txt.

Please see the documentation provided in docs/ for further
assistance with LLVM, and in particular docs/GettingStarted.rst for getting
started with LLVM and docs/README.txt for an overview of LLVM's
documentation setup.

If you're writing a package for LLVM, see docs/Packaging.rst for our
suggestions.
Description
LLVM backend for 6502
Readme 277 MiB
Languages
C++ 48.7%
LLVM 38.5%
Assembly 10.2%
C 0.9%
Python 0.4%
Other 1.2%