mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8a6f79e58d
Summary: Add numeric extend, trunctate to mips fast-isel Reactivates D4827 Test Plan: fpext.ll loadstoreconv.ll Reviewers: dsanders Subscribers: mcrosier Differential Revision: http://reviews.llvm.org/D5251 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218681 91177308-0d34-0410-b5e6-96231b3b80d8
574 lines
17 KiB
C++
574 lines
17 KiB
C++
//===-- MipsastISel.cpp - Mips FastISel implementation
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//---------------------===//
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/GlobalAlias.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLibraryInfo.h"
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#include "MipsRegisterInfo.h"
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#include "MipsISelLowering.h"
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#include "MipsMachineFunction.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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using namespace llvm;
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namespace {
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// All possible address modes.
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typedef struct Address {
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enum { RegBase, FrameIndexBase } BaseType;
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union {
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unsigned Reg;
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int FI;
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} Base;
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int64_t Offset;
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// Innocuous defaults for our address.
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Address() : BaseType(RegBase), Offset(0) { Base.Reg = 0; }
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} Address;
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class MipsFastISel final : public FastISel {
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/// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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Module &M;
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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const TargetLowering &TLI;
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const MipsSubtarget *Subtarget;
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MipsFunctionInfo *MFI;
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// Convenience variables to avoid some queries.
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LLVMContext *Context;
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bool TargetSupported;
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public:
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explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo)
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: FastISel(funcInfo, libInfo),
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M(const_cast<Module &>(*funcInfo.Fn->getParent())),
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TM(funcInfo.MF->getTarget()),
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TII(*TM.getSubtargetImpl()->getInstrInfo()),
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TLI(*TM.getSubtargetImpl()->getTargetLowering()),
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Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
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MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
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Context = &funcInfo.Fn->getContext();
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TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
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((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
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(Subtarget->isABI_O32())));
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}
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bool fastSelectInstruction(const Instruction *I) override;
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unsigned fastMaterializeConstant(const Constant *C) override;
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bool ComputeAddress(const Value *Obj, Address &Addr);
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private:
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bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
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unsigned Alignment = 0);
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bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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unsigned Alignment = 0);
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bool SelectLoad(const Instruction *I);
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bool SelectRet(const Instruction *I);
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bool SelectStore(const Instruction *I);
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bool SelectIntExt(const Instruction *I);
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bool SelectTrunc(const Instruction *I);
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bool SelectFPExt(const Instruction *I);
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bool isTypeLegal(Type *Ty, MVT &VT);
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bool isLoadTypeLegal(Type *Ty, MVT &VT);
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unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
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unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
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unsigned MaterializeInt(const Constant *C, MVT VT);
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unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
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bool EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
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bool IsZExt);
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bool EmitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
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bool EmitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
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bool EmitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg);
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bool EmitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg);
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// for some reason, this default is not generated by tablegen
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// so we explicitly generate it here.
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//
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unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill, uint64_t imm1,
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uint64_t imm2, unsigned Op3, bool Op3IsKill) {
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return 0;
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}
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MachineInstrBuilder EmitInst(unsigned Opc) {
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return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
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}
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MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) {
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return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
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DstReg);
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}
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MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg,
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unsigned MemReg, int64_t MemOffset) {
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return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
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}
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MachineInstrBuilder EmitInstLoad(unsigned Opc, unsigned DstReg,
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unsigned MemReg, int64_t MemOffset) {
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return EmitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
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}
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#include "MipsGenFastISel.inc"
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};
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bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
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EVT evt = TLI.getValueType(Ty, true);
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// Only handle simple types.
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if (evt == MVT::Other || !evt.isSimple())
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return false;
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VT = evt.getSimpleVT();
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// Handle all legal types, i.e. a register that will directly hold this
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// value.
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return TLI.isTypeLegal(VT);
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}
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bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
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if (isTypeLegal(Ty, VT))
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return true;
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// We will extend this in a later patch:
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// If this is a type than can be sign or zero-extended to a basic operation
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// go ahead and accept it now.
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if (VT == MVT::i8 || VT == MVT::i16)
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return true;
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return false;
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}
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bool MipsFastISel::ComputeAddress(const Value *Obj, Address &Addr) {
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// This construct looks a big awkward but it is how other ports handle this
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// and as this function is more fully completed, these cases which
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// return false will have additional code in them.
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//
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if (isa<Instruction>(Obj))
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return false;
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else if (isa<ConstantExpr>(Obj))
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return false;
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Addr.Base.Reg = getRegForValue(Obj);
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return Addr.Base.Reg != 0;
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}
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bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
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unsigned Alignment) {
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//
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// more cases will be handled here in following patches.
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//
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unsigned Opc;
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switch (VT.SimpleTy) {
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case MVT::i32: {
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ResultReg = createResultReg(&Mips::GPR32RegClass);
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Opc = Mips::LW;
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break;
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}
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case MVT::i16: {
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ResultReg = createResultReg(&Mips::GPR32RegClass);
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Opc = Mips::LHu;
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break;
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}
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case MVT::i8: {
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ResultReg = createResultReg(&Mips::GPR32RegClass);
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Opc = Mips::LBu;
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break;
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}
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case MVT::f32: {
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ResultReg = createResultReg(&Mips::FGR32RegClass);
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Opc = Mips::LWC1;
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break;
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}
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case MVT::f64: {
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ResultReg = createResultReg(&Mips::AFGR64RegClass);
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Opc = Mips::LDC1;
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break;
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}
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default:
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return false;
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}
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EmitInstLoad(Opc, ResultReg, Addr.Base.Reg, Addr.Offset);
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return true;
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}
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// Materialize a constant into a register, and return the register
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// number (or zero if we failed to handle it).
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unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
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EVT CEVT = TLI.getValueType(C->getType(), true);
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// Only handle simple types.
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if (!CEVT.isSimple())
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return 0;
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MVT VT = CEVT.getSimpleVT();
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if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
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return MaterializeFP(CFP, VT);
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else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
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return MaterializeGV(GV, VT);
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else if (isa<ConstantInt>(C))
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return MaterializeInt(C, VT);
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return 0;
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}
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bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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unsigned Alignment) {
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//
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// more cases will be handled here in following patches.
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//
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unsigned Opc;
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switch (VT.SimpleTy) {
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case MVT::i8:
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Opc = Mips::SB;
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break;
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case MVT::i16:
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Opc = Mips::SH;
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break;
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case MVT::i32:
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Opc = Mips::SW;
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break;
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case MVT::f32:
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Opc = Mips::SWC1;
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break;
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case MVT::f64:
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Opc = Mips::SDC1;
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break;
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default:
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return false;
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}
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EmitInstStore(Opc, SrcReg, Addr.Base.Reg, Addr.Offset);
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return true;
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}
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bool MipsFastISel::EmitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg) {
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unsigned ShiftAmt;
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switch (SrcVT.SimpleTy) {
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default:
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return false;
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case MVT::i8:
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ShiftAmt = 24;
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break;
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case MVT::i16:
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ShiftAmt = 16;
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break;
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}
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unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
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EmitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
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EmitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
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return true;
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}
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bool MipsFastISel::EmitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg) {
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switch (SrcVT.SimpleTy) {
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default:
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return false;
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case MVT::i8:
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EmitInst(Mips::SEB, DestReg).addReg(SrcReg);
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break;
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case MVT::i16:
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EmitInst(Mips::SEH, DestReg).addReg(SrcReg);
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break;
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}
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return true;
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}
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bool MipsFastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg, bool IsZExt) {
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if (IsZExt)
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return EmitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
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return EmitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
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}
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bool MipsFastISel::EmitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg) {
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if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
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return false;
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if (Subtarget->hasMips32r2())
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return EmitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
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return EmitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
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}
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bool MipsFastISel::EmitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg) {
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switch (SrcVT.SimpleTy) {
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default:
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return false;
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case MVT::i1:
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EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
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break;
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case MVT::i8:
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EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
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break;
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case MVT::i16:
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EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
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break;
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}
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return true;
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}
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bool MipsFastISel::SelectLoad(const Instruction *I) {
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// Atomic loads need special handling.
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if (cast<LoadInst>(I)->isAtomic())
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return false;
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// Verify we have a legal type before going any further.
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MVT VT;
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if (!isLoadTypeLegal(I->getType(), VT))
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return false;
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// See if we can handle this address.
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Address Addr;
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if (!ComputeAddress(I->getOperand(0), Addr))
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return false;
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unsigned ResultReg;
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if (!EmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
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return false;
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updateValueMap(I, ResultReg);
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return true;
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}
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bool MipsFastISel::SelectStore(const Instruction *I) {
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Value *Op0 = I->getOperand(0);
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unsigned SrcReg = 0;
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// Atomic stores need special handling.
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if (cast<StoreInst>(I)->isAtomic())
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return false;
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// Verify we have a legal type before going any further.
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MVT VT;
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if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
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return false;
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// Get the value to be stored into a register.
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SrcReg = getRegForValue(Op0);
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if (SrcReg == 0)
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return false;
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// See if we can handle this address.
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Address Addr;
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if (!ComputeAddress(I->getOperand(1), Addr))
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return false;
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if (!EmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
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return false;
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return true;
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}
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bool MipsFastISel::SelectRet(const Instruction *I) {
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const ReturnInst *Ret = cast<ReturnInst>(I);
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if (!FuncInfo.CanLowerReturn)
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return false;
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if (Ret->getNumOperands() > 0) {
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return false;
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}
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EmitInst(Mips::RetRA);
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return true;
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}
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// Attempt to fast-select a floating-point extend instruction.
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bool MipsFastISel::SelectFPExt(const Instruction *I) {
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Value *Src = I->getOperand(0);
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EVT SrcVT = TLI.getValueType(Src->getType(), true);
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EVT DestVT = TLI.getValueType(I->getType(), true);
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if (SrcVT != MVT::f32 || DestVT != MVT::f64)
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return false;
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unsigned SrcReg =
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getRegForValue(Src); // his must be a 32 bit floating point register class
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// maybe we should handle this differently
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if (!SrcReg)
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return false;
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unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
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EmitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
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updateValueMap(I, DestReg);
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return true;
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}
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bool MipsFastISel::SelectIntExt(const Instruction *I) {
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Type *DestTy = I->getType();
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Value *Src = I->getOperand(0);
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Type *SrcTy = Src->getType();
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bool isZExt = isa<ZExtInst>(I);
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unsigned SrcReg = getRegForValue(Src);
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if (!SrcReg)
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return false;
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EVT SrcEVT, DestEVT;
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SrcEVT = TLI.getValueType(SrcTy, true);
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DestEVT = TLI.getValueType(DestTy, true);
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if (!SrcEVT.isSimple())
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return false;
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if (!DestEVT.isSimple())
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return false;
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MVT SrcVT = SrcEVT.getSimpleVT();
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MVT DestVT = DestEVT.getSimpleVT();
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unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
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if (!EmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
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return false;
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updateValueMap(I, ResultReg);
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return true;
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}
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bool MipsFastISel::SelectTrunc(const Instruction *I) {
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// The high bits for a type smaller than the register size are assumed to be
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// undefined.
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Value *Op = I->getOperand(0);
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EVT SrcVT, DestVT;
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SrcVT = TLI.getValueType(Op->getType(), true);
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DestVT = TLI.getValueType(I->getType(), true);
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if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
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return false;
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if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
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return false;
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unsigned SrcReg = getRegForValue(Op);
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if (!SrcReg)
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return false;
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// Because the high bits are undefined, a truncate doesn't generate
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// any code.
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updateValueMap(I, SrcReg);
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return true;
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}
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bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
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if (!TargetSupported)
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return false;
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switch (I->getOpcode()) {
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default:
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break;
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case Instruction::Load:
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return SelectLoad(I);
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case Instruction::Store:
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return SelectStore(I);
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case Instruction::Ret:
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return SelectRet(I);
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case Instruction::Trunc:
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return SelectTrunc(I);
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case Instruction::ZExt:
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case Instruction::SExt:
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return SelectIntExt(I);
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case Instruction::FPExt:
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return SelectFPExt(I);
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}
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return false;
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}
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unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
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int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
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if (VT == MVT::f32) {
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const TargetRegisterClass *RC = &Mips::FGR32RegClass;
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unsigned DestReg = createResultReg(RC);
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unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
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EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
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return DestReg;
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} else if (VT == MVT::f64) {
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const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
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unsigned DestReg = createResultReg(RC);
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unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
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unsigned TempReg2 =
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Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
|
|
EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
|
|
return DestReg;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
|
|
// For now 32-bit only.
|
|
if (VT != MVT::i32)
|
|
return 0;
|
|
const TargetRegisterClass *RC = &Mips::GPR32RegClass;
|
|
unsigned DestReg = createResultReg(RC);
|
|
const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
|
|
bool IsThreadLocal = GVar && GVar->isThreadLocal();
|
|
// TLS not supported at this time.
|
|
if (IsThreadLocal)
|
|
return 0;
|
|
EmitInst(Mips::LW, DestReg)
|
|
.addReg(MFI->getGlobalBaseReg())
|
|
.addGlobalAddress(GV, 0, MipsII::MO_GOT);
|
|
if ((GV->hasInternalLinkage() ||
|
|
(GV->hasLocalLinkage() && !isa<Function>(GV)))) {
|
|
unsigned TempReg = createResultReg(RC);
|
|
EmitInst(Mips::ADDiu, TempReg)
|
|
.addReg(DestReg)
|
|
.addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
|
|
DestReg = TempReg;
|
|
}
|
|
return DestReg;
|
|
}
|
|
|
|
unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
|
|
if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
|
|
return 0;
|
|
const TargetRegisterClass *RC = &Mips::GPR32RegClass;
|
|
const ConstantInt *CI = cast<ConstantInt>(C);
|
|
int64_t Imm;
|
|
if ((VT != MVT::i1) && CI->isNegative())
|
|
Imm = CI->getSExtValue();
|
|
else
|
|
Imm = CI->getZExtValue();
|
|
return Materialize32BitInt(Imm, RC);
|
|
}
|
|
|
|
unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
|
|
const TargetRegisterClass *RC) {
|
|
unsigned ResultReg = createResultReg(RC);
|
|
|
|
if (isInt<16>(Imm)) {
|
|
unsigned Opc = Mips::ADDiu;
|
|
EmitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
|
|
return ResultReg;
|
|
} else if (isUInt<16>(Imm)) {
|
|
EmitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
|
|
return ResultReg;
|
|
}
|
|
unsigned Lo = Imm & 0xFFFF;
|
|
unsigned Hi = (Imm >> 16) & 0xFFFF;
|
|
if (Lo) {
|
|
// Both Lo and Hi have nonzero bits.
|
|
unsigned TmpReg = createResultReg(RC);
|
|
EmitInst(Mips::LUi, TmpReg).addImm(Hi);
|
|
EmitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
|
|
} else {
|
|
EmitInst(Mips::LUi, ResultReg).addImm(Hi);
|
|
}
|
|
return ResultReg;
|
|
}
|
|
}
|
|
|
|
namespace llvm {
|
|
FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
|
|
const TargetLibraryInfo *libInfo) {
|
|
return new MipsFastISel(funcInfo, libInfo);
|
|
}
|
|
}
|