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https://github.com/c64scene-ar/llvm-6502.git
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b53495606d
creation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218169 91177308-0d34-0410-b5e6-96231b3b80d8
221 lines
7.4 KiB
C++
221 lines
7.4 KiB
C++
//===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the Mips specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsMachineFunction.h"
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#include "Mips.h"
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#include "MipsRegisterInfo.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "mips-subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "MipsGenSubtargetInfo.inc"
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// FIXME: Maybe this should be on by default when Mips16 is specified
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//
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static cl::opt<bool> Mixed16_32(
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"mips-mixed-16-32",
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cl::init(false),
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cl::desc("Allow for a mixture of Mips16 "
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"and Mips32 code in a single source file"),
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cl::Hidden);
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static cl::opt<bool> Mips_Os16(
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"mips-os16",
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cl::init(false),
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cl::desc("Compile all functions that don' use "
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"floating point as Mips 16"),
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cl::Hidden);
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static cl::opt<bool>
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Mips16HardFloat("mips16-hard-float", cl::NotHidden,
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cl::desc("MIPS: mips16 hard float enable."),
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cl::init(false));
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static cl::opt<bool>
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Mips16ConstantIslands(
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"mips16-constant-islands", cl::NotHidden,
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cl::desc("MIPS: mips16 constant islands enable."),
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cl::init(true));
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/// Select the Mips CPU for the given triple and cpu name.
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/// FIXME: Merge with the copy in MipsMCTargetDesc.cpp
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static StringRef selectMipsCPU(Triple TT, StringRef CPU) {
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if (CPU.empty() || CPU == "generic") {
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if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
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CPU = "mips32";
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else
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CPU = "mips64";
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}
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return CPU;
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}
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void MipsSubtarget::anchor() { }
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static std::string computeDataLayout(const MipsSubtarget &ST) {
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std::string Ret = "";
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// There are both little and big endian mips.
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if (ST.isLittle())
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Ret += "e";
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else
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Ret += "E";
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Ret += "-m:m";
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// Pointers are 32 bit on some ABIs.
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if (!ST.isABI_N64())
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Ret += "-p:32:32";
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// 8 and 16 bit integers only need no have natural alignment, but try to
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// align them to 32 bits. 64 bit integers have natural alignment.
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Ret += "-i8:8:32-i16:16:32-i64:64";
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// 32 bit registers are always available and the stack is at least 64 bit
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// aligned. On N64 64 bit registers are also available and the stack is
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// 128 bit aligned.
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if (ST.isABI_N64() || ST.isABI_N32())
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Ret += "-n32:64-S128";
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else
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Ret += "-n32-S64";
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return Ret;
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}
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MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS, bool little,
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const MipsTargetMachine *_TM)
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: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
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MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
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IsFPXX(false), NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
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IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
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IsLinux(true), HasMips3_32(false), HasMips3_32r2(false),
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HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
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InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
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InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
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AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
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HasMSA(false), TM(_TM), TargetTriple(TT),
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DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))),
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TSInfo(DL), InstrInfo(MipsInstrInfo::create(*this)),
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FrameLowering(MipsFrameLowering::create(*this)),
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TLInfo(MipsTargetLowering::create(*TM, *this)) {
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PreviousInMips16Mode = InMips16Mode;
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// Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and
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// MIPS-V. They have not been tested and currently exist for the integrated
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// assembler only.
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if (MipsArchVersion == Mips1)
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report_fatal_error("Code generation for MIPS-I is not implemented", false);
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if (MipsArchVersion == Mips2)
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report_fatal_error("Code generation for MIPS-II is not implemented", false);
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if (MipsArchVersion == Mips3)
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report_fatal_error("Code generation for MIPS-III is not implemented",
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false);
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if (MipsArchVersion == Mips5)
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report_fatal_error("Code generation for MIPS-V is not implemented", false);
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// Assert exactly one ABI was chosen.
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assert(MipsABI != UnknownABI);
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assert((((getFeatureBits() & Mips::FeatureO32) != 0) +
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((getFeatureBits() & Mips::FeatureEABI) != 0) +
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((getFeatureBits() & Mips::FeatureN32) != 0) +
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((getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
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// Check if Architecture and ABI are compatible.
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assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
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(isGP64bit() && (isABI_N32() || isABI_N64()))) &&
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"Invalid Arch & ABI pair.");
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if (hasMSA() && !isFP64bit())
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report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
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"See -mattr=+fp64.",
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false);
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if (!isABI_O32() && !useOddSPReg())
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report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
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if (IsFPXX && (isABI_N32() || isABI_N64()))
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report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
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if (hasMips32r6()) {
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StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
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assert(isFP64bit());
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assert(isNaN2008());
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if (hasDSP())
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report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
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}
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// Is the target system Linux ?
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if (TT.find("linux") == std::string::npos)
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IsLinux = false;
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// Set UseSmallSection.
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// TODO: Investigate the IsLinux check. I suspect it's really checking for
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// bare-metal.
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UseSmallSection = !IsLinux && (TM->getRelocationModel() == Reloc::Static);
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}
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/// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
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bool MipsSubtarget::enablePostMachineScheduler() const { return true; }
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void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
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CriticalPathRCs.clear();
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CriticalPathRCs.push_back(isGP64bit() ?
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&Mips::GPR64RegClass : &Mips::GPR32RegClass);
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}
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CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
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return CodeGenOpt::Aggressive;
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}
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MipsSubtarget &
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MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
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const TargetMachine *TM) {
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std::string CPUName = selectMipsCPU(TargetTriple, CPU);
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// Parse features string.
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ParseSubtargetFeatures(CPUName, FS);
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUName);
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if (InMips16Mode && !TM->Options.UseSoftFloat)
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InMips16HardFloat = true;
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return *this;
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}
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bool MipsSubtarget::abiUsesSoftFloat() const {
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return TM->Options.UseSoftFloat && !InMips16HardFloat;
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}
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bool MipsSubtarget::useConstantIslands() {
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DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
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return Mips16ConstantIslands;
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}
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Reloc::Model MipsSubtarget::getRelocationModel() const {
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return TM->getRelocationModel();
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}
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