Bill Wendling 3b1259bb9f "The instructions MMX_PSADBWrm and MMX_PSADBWrr have opcode 0b11100000 (e0), but ... the Intel manual (screenshot) says it should be 0b11110110 (f6). The existing encoding causes a disassembly conflict with MMX_PAVGBrm, which really should be 0f e0." Patch by Sean Callanan! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72508 91177308-0d34-0410-b5e6-96231b3b80d8		2009-05-28 02:04:00 +00:00
..
Analysis	Add braces around an array initializer.	2009-05-27 02:07:15 +00:00
Archive
AsmParser	Use v.data() instead of &v[0] when SmallVector v might be empty.	2009-05-21 09:52:38 +00:00
Bitcode
CodeGen	Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.	2009-05-28 00:35:15 +00:00
CompilerDriver
Debugger
ExecutionEngine	stat64/open64/lseek64 for the interpreter	2009-05-23 16:23:59 +00:00
Linker
Support	Minor fix for CMake build system	2009-05-27 16:52:17 +00:00
System	Work around a page size issue on Cygwin.	2009-05-23 17:57:59 +00:00
Target	"The instructions MMX_PSADBWrm and MMX_PSADBWrr have opcode 0b11100000 (e0), but	2009-05-28 02:04:00 +00:00
Transforms	Revert 72493 and replace it with a more conservative fix, for now: don't	2009-05-27 21:10:47 +00:00
VMCore	Audit the type constructors. Previously it was possible to create [0 x void]	2009-05-25 21:28:11 +00:00
Makefile