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https://github.com/c64scene-ar/llvm-6502.git
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3b79f0ccc3
Summary: Previously, we would sign-extend non-boolean negative constants and zero-extend otherwise. This was problematic for PHI instructions with negative values that had a type with bitwidth less than that of the register used for materialization. More specifically, ComputePHILiveOutRegInfo() assumes the constants present in a PHI node are zero extended in their container and afterwards deduces the known bits. For example, previously we would materialize an i16 -4 with the following instruction: addiu $r, $zero, -4 The register would end-up with the 32-bit 2's complement representation of -4. However, ComputePHILiveOutRegInfo() would generate a constant with the upper 16-bits set to zero. The SelectionDAG builder would use that information to generate an AssertZero node that would remove any subsequent trunc & zero_extend nodes. In theory, we should modify ComputePHILiveOutRegInfo() to consult target-specific hooks about the way they prefer to materialize the given constants. However, git-blame reports that this specific code has not been touched since 2011 and it seems to be working well for every target so far. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243636 91177308-0d34-0410-b5e6-96231b3b80d8
69 lines
2.1 KiB
LLVM
69 lines
2.1 KiB
LLVM
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
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; RUN: < %s | FileCheck %s
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@ijk = external global i32
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; Function Attrs: nounwind
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define void @si2_1() #0 {
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entry:
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store i32 32767, i32* @ijk, align 4
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; CHECK: .ent si2_1
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; CHECK: addiu $[[REG1:[0-9]+]], $zero, 32767
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; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
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; CHECK: sw $[[REG1]], 0($[[REG2]])
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ret void
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}
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; Function Attrs: nounwind
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define void @si2_2() #0 {
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entry:
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store i32 -32768, i32* @ijk, align 4
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; CHECK: .ent si2_2
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; CHECK: lui $[[REG1:[0-9]+]], 65535
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; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 32768
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; CHECK: lw $[[REG3:[0-9]+]], %got(ijk)(${{[0-9]+}})
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; CHECK: sw $[[REG2]], 0($[[REG3]])
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ret void
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}
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; Function Attrs: nounwind
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define void @ui2_1() #0 {
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entry:
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store i32 65535, i32* @ijk, align 4
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; CHECK: .ent ui2_1
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; CHECK: ori $[[REG1:[0-9]+]], $zero, 65535
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; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
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; CHECK: sw $[[REG1]], 0($[[REG2]])
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ret void
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}
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; Function Attrs: nounwind
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define void @ui4_1() #0 {
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entry:
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store i32 983040, i32* @ijk, align 4
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; CHECK: .ent ui4_1
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; CHECK: lui $[[REG1:[0-9]+]], 15
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; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
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; CHECK: sw $[[REG1]], 0($[[REG2]])
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ret void
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}
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; Function Attrs: nounwind
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define void @ui4_2() #0 {
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entry:
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store i32 719566, i32* @ijk, align 4
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; CHECK: .ent ui4_2
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; CHECK: lui $[[REG1:[0-9]+]], 10
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; CHECK: ori $[[REG1]], $[[REG1]], 64206
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; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
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; CHECK: sw $[[REG1]], 0($[[REG2]])
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ret void
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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