llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-16 14:31:59 +00:00

History

Kevin Qin f14f22cebf [AArch64 NEON] Fix invalid constant used in vselect condition.

There is a wrong assumption that the vector element type and the
type of each ConstantSDNode in the build_vector were the same.
However, when promoting the integer operand of a legally typed
build_vector, the operand type and the vector element type do not
need to be the same
(See method 'DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR' in
LegalizeIntegerTypes.cpp).

  in AArch64 backend, the following dag sequence:

  C0: i1 = Constant<0>
  C1: i1 = Constant<-1>
  V: v8i1 = BUILD_VECTOR C1, C1, C0, C0, C0, C0, C0, C0

  is type-legalized into:

  NewC0: i32 = Constant<0>
  NewC1: i32 = Constant<1>
  V: v8i8 = BUILD_VECTOR NewC1, NewC1, NewC0, NewC0, NewC0, NewC0, NewC0, NewC0

Forcing a getZeroExtend to VTBits to ensure that the new constant
is correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198582 91177308-0d34-0410-b5e6-96231b3b80d8

2014-01-06 02:26:10 +00:00

Analysis

BasicAA: Use reachabilty instead of dominance for checking value equality in phi

2014-01-03 05:47:03 +00:00

Assembler

Allow addrspacecast in global aliases

2014-01-02 20:55:01 +00:00

Bindings

Update the ML test to expect the new string format of getStringRepresentation.

2013-12-19 23:38:09 +00:00

Bitcode

Fold vector selects with undef elements in the condition. Fixes PR18319.