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https://github.com/c64scene-ar/llvm-6502.git
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f5c04a9da7
as it caused miscompilations and assertion failures (PR23768, http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150601/280380.html). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239169 91177308-0d34-0410-b5e6-96231b3b80d8
278 lines
9.6 KiB
C++
278 lines
9.6 KiB
C++
//===-- ARMSelectionDAGInfo.cpp - ARM SelectionDAG Info -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ARMSelectionDAGInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMTargetMachine.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/IR/DerivedTypes.h"
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using namespace llvm;
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#define DEBUG_TYPE "arm-selectiondag-info"
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ARMSelectionDAGInfo::ARMSelectionDAGInfo(const DataLayout &DL)
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: TargetSelectionDAGInfo(&DL) {}
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ARMSelectionDAGInfo::~ARMSelectionDAGInfo() {
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}
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// Emit, if possible, a specialized version of the given Libcall. Typically this
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// means selecting the appropriately aligned version, but we also convert memset
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// of 0 into memclr.
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SDValue ARMSelectionDAGInfo::
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EmitSpecializedLibcall(SelectionDAG &DAG, SDLoc dl,
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SDValue Chain,
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SDValue Dst, SDValue Src,
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SDValue Size, unsigned Align,
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RTLIB::Libcall LC) const {
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const ARMSubtarget &Subtarget =
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DAG.getMachineFunction().getSubtarget<ARMSubtarget>();
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const ARMTargetLowering *TLI = Subtarget.getTargetLowering();
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// Only use a specialized AEABI function if the default version of this
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// Libcall is an AEABI function.
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if (std::strncmp(TLI->getLibcallName(LC), "__aeabi", 7) != 0)
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return SDValue();
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// Translate RTLIB::Libcall to AEABILibcall. We only do this in order to be
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// able to translate memset to memclr and use the value to index the function
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// name array.
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enum {
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AEABI_MEMCPY = 0,
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AEABI_MEMMOVE,
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AEABI_MEMSET,
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AEABI_MEMCLR
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} AEABILibcall;
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switch (LC) {
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case RTLIB::MEMCPY:
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AEABILibcall = AEABI_MEMCPY;
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break;
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case RTLIB::MEMMOVE:
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AEABILibcall = AEABI_MEMMOVE;
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break;
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case RTLIB::MEMSET:
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AEABILibcall = AEABI_MEMSET;
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if (ConstantSDNode *ConstantSrc = dyn_cast<ConstantSDNode>(Src))
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if (ConstantSrc->getZExtValue() == 0)
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AEABILibcall = AEABI_MEMCLR;
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break;
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default:
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return SDValue();
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}
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// Choose the most-aligned libcall variant that we can
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enum {
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ALIGN1 = 0,
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ALIGN4,
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ALIGN8
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} AlignVariant;
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if ((Align & 7) == 0)
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AlignVariant = ALIGN8;
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else if ((Align & 3) == 0)
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AlignVariant = ALIGN4;
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else
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AlignVariant = ALIGN1;
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TargetLowering::ArgListTy Args;
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TargetLowering::ArgListEntry Entry;
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Entry.Ty = TLI->getDataLayout()->getIntPtrType(*DAG.getContext());
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Entry.Node = Dst;
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Args.push_back(Entry);
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if (AEABILibcall == AEABI_MEMCLR) {
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Entry.Node = Size;
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Args.push_back(Entry);
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} else if (AEABILibcall == AEABI_MEMSET) {
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// Adjust parameters for memset, EABI uses format (ptr, size, value),
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// GNU library uses (ptr, value, size)
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// See RTABI section 4.3.4
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Entry.Node = Size;
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Args.push_back(Entry);
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// Extend or truncate the argument to be an i32 value for the call.
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if (Src.getValueType().bitsGT(MVT::i32))
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Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
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else if (Src.getValueType().bitsLT(MVT::i32))
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Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
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Entry.Node = Src;
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Entry.Ty = Type::getInt32Ty(*DAG.getContext());
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Entry.isSExt = false;
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Args.push_back(Entry);
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} else {
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Entry.Node = Src;
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Args.push_back(Entry);
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Entry.Node = Size;
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Args.push_back(Entry);
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}
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char const *FunctionNames[4][3] = {
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{ "__aeabi_memcpy", "__aeabi_memcpy4", "__aeabi_memcpy8" },
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{ "__aeabi_memmove", "__aeabi_memmove4", "__aeabi_memmove8" },
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{ "__aeabi_memset", "__aeabi_memset4", "__aeabi_memset8" },
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{ "__aeabi_memclr", "__aeabi_memclr4", "__aeabi_memclr8" }
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};
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TargetLowering::CallLoweringInfo CLI(DAG);
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CLI.setDebugLoc(dl).setChain(Chain)
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.setCallee(TLI->getLibcallCallingConv(LC),
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Type::getVoidTy(*DAG.getContext()),
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DAG.getExternalSymbol(FunctionNames[AEABILibcall][AlignVariant],
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TLI->getPointerTy()), std::move(Args), 0)
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.setDiscardResult();
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std::pair<SDValue,SDValue> CallResult = TLI->LowerCallTo(CLI);
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return CallResult.second;
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}
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SDValue
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ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
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SDValue Chain,
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SDValue Dst, SDValue Src,
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SDValue Size, unsigned Align,
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bool isVolatile, bool AlwaysInline,
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MachinePointerInfo DstPtrInfo,
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MachinePointerInfo SrcPtrInfo) const {
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const ARMSubtarget &Subtarget =
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DAG.getMachineFunction().getSubtarget<ARMSubtarget>();
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// Do repeated 4-byte loads and stores. To be improved.
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// This requires 4-byte alignment.
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if ((Align & 3) != 0)
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return SDValue();
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// This requires the copy size to be a constant, preferably
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// within a subtarget-specific limit.
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ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
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if (!ConstantSize)
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return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size, Align,
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RTLIB::MEMCPY);
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uint64_t SizeVal = ConstantSize->getZExtValue();
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if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold())
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return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size, Align,
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RTLIB::MEMCPY);
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unsigned BytesLeft = SizeVal & 3;
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unsigned NumMemOps = SizeVal >> 2;
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unsigned EmittedNumMemOps = 0;
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EVT VT = MVT::i32;
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unsigned VTSize = 4;
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unsigned i = 0;
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// Emit a maximum of 4 loads in Thumb1 since we have fewer registers
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const unsigned MAX_LOADS_IN_LDM = Subtarget.isThumb1Only() ? 4 : 6;
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SDValue TFOps[6];
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SDValue Loads[6];
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uint64_t SrcOff = 0, DstOff = 0;
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// Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
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// same number of stores. The loads and stores will get combined into
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// ldm/stm later on.
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while (EmittedNumMemOps < NumMemOps) {
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for (i = 0;
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i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
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Loads[i] = DAG.getLoad(VT, dl, Chain,
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DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
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DAG.getConstant(SrcOff, dl, MVT::i32)),
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SrcPtrInfo.getWithOffset(SrcOff), isVolatile,
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false, false, 0);
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TFOps[i] = Loads[i].getValue(1);
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SrcOff += VTSize;
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}
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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makeArrayRef(TFOps, i));
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for (i = 0;
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i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
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TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
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DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
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DAG.getConstant(DstOff, dl, MVT::i32)),
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DstPtrInfo.getWithOffset(DstOff),
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isVolatile, false, 0);
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DstOff += VTSize;
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}
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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makeArrayRef(TFOps, i));
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EmittedNumMemOps += i;
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}
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if (BytesLeft == 0)
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return Chain;
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// Issue loads / stores for the trailing (1 - 3) bytes.
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unsigned BytesLeftSave = BytesLeft;
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i = 0;
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while (BytesLeft) {
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if (BytesLeft >= 2) {
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VT = MVT::i16;
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VTSize = 2;
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} else {
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VT = MVT::i8;
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VTSize = 1;
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}
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Loads[i] = DAG.getLoad(VT, dl, Chain,
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DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
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DAG.getConstant(SrcOff, dl, MVT::i32)),
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SrcPtrInfo.getWithOffset(SrcOff),
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false, false, false, 0);
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TFOps[i] = Loads[i].getValue(1);
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++i;
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SrcOff += VTSize;
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BytesLeft -= VTSize;
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}
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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makeArrayRef(TFOps, i));
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i = 0;
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BytesLeft = BytesLeftSave;
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while (BytesLeft) {
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if (BytesLeft >= 2) {
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VT = MVT::i16;
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VTSize = 2;
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} else {
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VT = MVT::i8;
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VTSize = 1;
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}
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TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
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DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
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DAG.getConstant(DstOff, dl, MVT::i32)),
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DstPtrInfo.getWithOffset(DstOff), false, false, 0);
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++i;
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DstOff += VTSize;
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BytesLeft -= VTSize;
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}
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return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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makeArrayRef(TFOps, i));
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}
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SDValue ARMSelectionDAGInfo::
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EmitTargetCodeForMemmove(SelectionDAG &DAG, SDLoc dl,
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SDValue Chain,
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SDValue Dst, SDValue Src,
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SDValue Size, unsigned Align,
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bool isVolatile,
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MachinePointerInfo DstPtrInfo,
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MachinePointerInfo SrcPtrInfo) const {
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return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size, Align,
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RTLIB::MEMMOVE);
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}
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SDValue ARMSelectionDAGInfo::
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EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
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SDValue Chain, SDValue Dst,
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SDValue Src, SDValue Size,
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unsigned Align, bool isVolatile,
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MachinePointerInfo DstPtrInfo) const {
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return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size, Align,
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RTLIB::MEMSET);
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}
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