Elena Demikhovsky 3d1ae71813 AVX-512: masked load/store + intrinsics for them. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203790 91177308-0d34-0410-b5e6-96231b3b80d8

2014-03-13 12:05:52 +00:00

..

AArch64

IR: add a second ordering operand to cmpxhg for failure

2014-03-11 10:48:52 +00:00

ARM

ARM: correct Dwarf output for non-contiguous VFP saves.

2014-03-12 11:29:23 +00:00

CPP

Begin adding docs and IR-level support for the inalloca attribute

2013-12-19 02:14:12 +00:00

Generic

CommandLine: Exit successfully for -version and -help

2014-02-28 19:08:01 +00:00

Hexagon

Fix broken CHECK lines

2014-02-16 07:31:05 +00:00

Inputs

Debug Info: update testing cases to specify the debug info version number.

2013-11-22 21:49:45 +00:00

Mips

[mips] BSEL's and BINS[RL] operands are reversed compared to the vselect node used in the pattern.

2014-03-12 11:54:00 +00:00

MSP430

Fix known typos

2014-01-24 17:20:08 +00:00

NVPTX

Followup to r203483 - add test.

2014-03-10 20:36:04 +00:00

PowerPC

[PowerPC] Initial support for the VSX instruction set

2014-03-13 07:58:58 +00:00

R600

R600: Fix trunc store from i64 to i1

2014-03-12 18:45:52 +00:00

SPARC

IR: add a second ordering operand to cmpxhg for failure

2014-03-11 10:48:52 +00:00

SystemZ

IR: add a second ordering operand to cmpxhg for failure

2014-03-11 10:48:52 +00:00

Thumb

Add triples to try to fix the windows bots.

2014-02-13 16:49:47 +00:00

Thumb2

ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block

2014-02-26 11:27:28 +00:00

X86

AVX-512: masked load/store + intrinsics for them.

2014-03-13 12:05:52 +00:00

XCore

[XCore] Add support for the "m" inline asm constraint.

2014-03-06 16:37:48 +00:00