mirror of
https://github.com/c64scene-ar/llvm-6502.git
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eecdb661ec
SparcInstrSelection.cpp:
* Fixed opcodes to return correct 'i' version since the two functions are each
only used in one place.
* Changed name of function to have an 'i' in the name to signify that they each
return an immediate form of the opcode.
* Added a warning if either of the functions is ever used in a context which
requires a register-version opcode.
SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing
SparcV9.td: added the MOV(F)cc instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6548 91177308-0d34-0410-b5e6-96231b3b80d8
123 lines
2.7 KiB
C++
123 lines
2.7 KiB
C++
//===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
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// vim:ft=cpp
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//===----------------------------------------------------------------------===//
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//----------------------- F4 classes -----------------------------------------
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// F4 - Common superclass of all F4 instructions. All instructions have an op3
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// field.
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class F4 : InstV9 {
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bits<6> op3;
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set Inst{24-19} = op3;
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}
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class F4_rd : F4 {
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bits<5> rd;
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set Inst{29-25} = rd;
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}
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class F4_rdsimm11 : F4_rd {
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bits<11> simm11;
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set Inst{10-0} = simm11;
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}
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class F4_rdsimm11rs1 : F4_rdsimm11 {
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bits<5> rs1;
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set Inst{18-14} = rs1;
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}
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// F4_rdrs1 - Common superclass of instructions that use rd & rs1
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class F4_rdrs1 : F4_rd {
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bits<5> rs1;
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set Inst{18-14} = rs1;
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}
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// F4_rs1rdrs2 - Common superclass of instructions with rd, rs1, & rs2 fields
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class F4_rdrs1rs2 : F4_rdrs1 {
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bits<5> rs2;
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set Inst{4-0} = rs2;
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}
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// F4_rs1 - Common class of instructions that do not have an rd field,
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// but start at rs1
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class F4_rs1 : F4 {
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bits<5> rs1;
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//set Inst{29-25} = dontcare;
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set Inst{18-14} = rs1;
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}
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// F4_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
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class F4_rs1rs2 : F4_rs1 {
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bits<5> rs2;
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//set Inst{12-5} = dontcare;
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set Inst{4-0} = rs2;
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}
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// F4_cc - Common class of instructions that have a cond field
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class F4_cond : F4 {
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bits<4> cond;
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set Inst{17-14} = cond;
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}
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// F4_cc - Common class of instructions that have cc register as first operand
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class F4_condcc : F4_cond {
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bits<3> cc;
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set Inst{18} = cc{2};
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set Inst{12} = cc{1};
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set Inst{11} = cc{0};
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}
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// Actual F4 instruction classes
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// FIXME: order of operands is incorrect!!
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class F4_1<bits<2> opVal, bits<6> op3Val, string name> : F4_rdrs1rs2 {
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bits<2> cc;
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set op = opVal;
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set op3 = op3Val;
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set Name = name;
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set Inst{13} = 0; // i bit
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set Inst{12-11} = cc;
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//set Inst{10-5} = dontcare;
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}
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// FIXME: order of operands is incorrect!!
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class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rdsimm11rs1 {
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bits<2> cc;
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set op = opVal;
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set op3 = op3Val;
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set Name = name;
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set Inst{13} = 1; // i bit
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set Inst{12-11} = cc;
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}
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class F4_3<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
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string name> : F4_condcc {
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bits<5> rs2;
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set op = opVal;
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set op3 = op3Val;
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set cond = condVal;
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set Name = name;
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set Inst{13} = 0; // i bit
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//set Inst{10-5} = dontcare;
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set Inst{4-0} = rs2;
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}
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class F4_4<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
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string name> : F4_condcc {
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bits<11> sim11;
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bits<5> rd;
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set op = opVal;
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set op3 = op3Val;
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set cond = condVal;
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set Name = name;
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set Inst{13} = 1; // i bit
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set Inst{10-0} = sim11;
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}
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// FIXME: F4 classes 4
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