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https://github.com/c64scene-ar/llvm-6502.git
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69261a6442
the alignment is clamped to TargetFrameLowering.getStackAlignment if the target does not support stack realignment or the option "realign-stack" is off. This will cause miscompile if the address is treated as aligned and add is replaced with or in DAGCombine. Added a bool StackRealignable to TargetFrameLowering to check whether stack realignment is implemented for the target. Also added a bool RealignOption to MachineFrameInfo to check whether the option "realign-stack" is on. rdar://12713765 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169197 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
1.6 KiB
LLVM
49 lines
1.6 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-ios -O0 -realign-stack=0 | FileCheck %s -check-prefix=NO-REALIGN
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; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s
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; rdar://12713765
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; When realign-stack is set to false, make sure we are not creating stack
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; objects that are assumed to be 64-byte aligned.
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@T3_retval = common global <16 x float> zeroinitializer, align 16
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define void @test(<16 x float>* noalias sret %agg.result) nounwind ssp {
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entry:
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; CHECK: test
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; CHECK: bic sp, sp, #63
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; CHECK: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48
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; CHECK: vst1.64
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; CHECK: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32
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; CHECK: vst1.64
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; CHECK: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16
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; CHECK: vst1.64
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; CHECK: vst1.64
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; CHECK: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48
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; CHECK: vst1.64
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; CHECK: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32
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; CHECK: vst1.64
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; CHECK: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16
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; CHECK: vst1.64
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; CHECK: vst1.64
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; NO-REALIGN: test
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; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48
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; NO-REALIGN: vst1.64
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; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32
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; NO-REALIGN: vst1.64
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; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16
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; NO-REALIGN: vst1.64
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; NO-REALIGN: vst1.64
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; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48
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; NO-REALIGN: vst1.64
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; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32
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; NO-REALIGN: vst1.64
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; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16
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; NO-REALIGN: vst1.64
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; NO-REALIGN: vst1.64
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%retval = alloca <16 x float>, align 16
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%0 = load <16 x float>* @T3_retval, align 16
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store <16 x float> %0, <16 x float>* %retval
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%1 = load <16 x float>* %retval
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store <16 x float> %1, <16 x float>* %agg.result, align 16
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ret void
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}
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