Chandler Carruth 3e990c1e5b [x86] Actually test the SSE2 lowering for most of the zext-ish shuffles. ...

Not sure why I only did SSSE3 here. Also, I've left out some of the SSE2
ones because the shuffles are so absurd it's not worth transcribing
them. Will try to fix them to be sane and then check them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218114 91177308-0d34-0410-b5e6-96231b3b80d8

2014-09-19 08:51:06 +00:00

..

AArch64

Optimize sext/zext insertion algorithm in back-end.

2014-09-19 05:30:35 +00:00

ARM

[ARM] Do not perform a tail call when the caller returns several values.

2014-09-18 21:17:50 +00:00

CPP

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Generic

Add a regression test to sanity check the PBQP allocator.

2014-09-03 18:04:10 +00:00

Hexagon

DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.

2014-08-06 00:21:25 +00:00

Inputs

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Mips

Add mips32 r1 to the list of supported targets for Mips fast-isel

2014-09-15 20:30:25 +00:00

MSP430

Drop the W postfix on the 16-bit registers.

2014-09-10 06:58:14 +00:00

NVPTX

[MachineSink] Use the real post dominator tree

2014-09-01 03:47:25 +00:00

PowerPC

Fix FastISel bug in boolean returns for PowerPC.

2014-09-17 23:25:06 +00:00

R600

R600: Better fix for bug 20982

2014-09-19 00:42:06 +00:00

SPARC

Add back tests for empty function in SPARC and PowerPC.

2014-09-15 22:11:07 +00:00

SystemZ

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Thumb

Check-label a bit more specific

2014-09-03 13:32:08 +00:00

Thumb2

ARM / x86_64 varargs: Don't save regparms in prologue without va_start

2014-08-22 21:59:26 +00:00

X86

[x86] Actually test the SSE2 lowering for most of the zext-ish shuffles.

2014-09-19 08:51:06 +00:00

XCore

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