Oliver Stannard e7c9c44387 [Thumb2] RFE, SRS and "SUBS pc, lr" are undefined on v7M ...

These instructions are related to the v7[AR] exception model, and are
not defined on v7M.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220204 91177308-0d34-0410-b5e6-96231b3b80d8

2014-10-20 15:37:35 +00:00

..

AArch64

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ARM

[Thumb2] RFE, SRS and "SUBS pc, lr" are undefined on v7M

2014-10-20 15:37:35 +00:00

AsmParser

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COFF

MC, COFF: Make bigobj test compatible with python3

2014-10-14 22:35:11 +00:00

Disassembler

[X86] Fix a bug where the disassembler was ignoring the VEX.W bit in 32-bit mode for certain instructions it shouldn't.

2014-10-07 07:29:50 +00:00

ELF

Add back commits r219835 and a fixed version of r219829.

2014-10-17 01:48:58 +00:00

MachO

MachObjectWriter: optimize the string table for common suffices

2014-10-06 17:05:19 +00:00

Markup

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Mips

[mips] Add support for COP1's Branch-On-Cond-Likely instructions

2014-10-17 14:08:28 +00:00

PowerPC

[PPC64] VSX indexed-form loads use wrong instruction format

2014-10-09 17:51:35 +00:00

Sparc

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SystemZ

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X86

[AVX512] Add DQ subvector inserts

2014-10-15 23:42:17 +00:00