mirror of
https://github.com/c64scene-ar/llvm-6502.git
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99c372e723
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83487 91177308-0d34-0410-b5e6-96231b3b80d8
114 lines
3.1 KiB
LLVM
114 lines
3.1 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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; This tests icmp operations that do not map directly to NEON instructions.
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; Not-equal (ne) operations are implemented by VCEQ/VMVN. Less-than (lt/ult)
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; and less-than-or-equal (le/ule) are implemented by swapping the arguments
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; to VCGT and VCGE. Test all the operand types for not-equal but only sample
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; the other operations.
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define <8 x i8> @vcnei8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vcnei8:
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;CHECK: vceq.i8
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;CHECK-NEXT: vmvn
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = icmp ne <8 x i8> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vcnei16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vcnei16:
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;CHECK: vceq.i16
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;CHECK-NEXT: vmvn
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = icmp ne <4 x i16> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vcnei32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vcnei32:
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;CHECK: vceq.i32
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;CHECK-NEXT: vmvn
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = icmp ne <2 x i32> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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define <16 x i8> @vcneQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vcneQi8:
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;CHECK: vceq.i8
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;CHECK-NEXT: vmvn
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = icmp ne <16 x i8> %tmp1, %tmp2
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%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vcneQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vcneQi16:
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;CHECK: vceq.i16
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;CHECK-NEXT: vmvn
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = icmp ne <8 x i16> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vcneQi32:
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;CHECK: vceq.i32
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;CHECK-NEXT: vmvn
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = icmp ne <4 x i32> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
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ret <4 x i32> %tmp4
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}
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define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vcltQs8:
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;CHECK: vcgt.s8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = icmp slt <16 x i8> %tmp1, %tmp2
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%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
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ret <16 x i8> %tmp4
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}
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define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vcles16:
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;CHECK: vcge.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = icmp sle <4 x i16> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
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ret <4 x i16> %tmp4
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}
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define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vcltu16:
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;CHECK: vcgt.u16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = icmp ult <4 x i16> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
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ret <4 x i16> %tmp4
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}
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define <4 x i32> @vcleQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vcleQu32:
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;CHECK: vcge.u32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = icmp ule <4 x i32> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
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ret <4 x i32> %tmp4
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}
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