This website requires JavaScript.
Explore
Mirrors
Help
Sign In
6502
/
llvm-6502
Watch
1
Star
0
Fork
0
You've already forked llvm-6502
mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced
2025-01-05 12:31:33 +00:00
Code
Issues
Projects
Releases
Wiki
Activity
407014f9a5
llvm-6502
/
include
/
llvm
/
Target
History
Daniel Dunbar
cbe762b5d1
Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.
...
git-svn-id:
https://llvm.org/svn/llvm-project/llvm/trunk@106634
91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 17:09:26 +00:00
..
Mangler.h
SubtargetFeature.h
Target.td
Remove isTwoAddress from llvm.
2010-06-21 20:35:09 +00:00
TargetAsmBackend.h
MC: Change RelaxInstruction to only take the input and output instructions.
2010-05-26 18:15:06 +00:00
TargetAsmLexer.h
TargetAsmParser.h
TargetCallingConv.td
Add 'Indirect' LocInfo class and use to pass __m128 on win64. Also minore fixes here and there (mostly __m64).
2009-08-03 08:13:56 +00:00
TargetData.h
Revert r97064. Duncan pointed out that bitcasts are defined in
2010-02-25 15:20:39 +00:00
TargetELFWriterInfo.h
TargetFrameInfo.h
TargetInstrDesc.h
Start TargetRegisterClass indices at 0 instead of 1, so that
2010-06-18 18:13:55 +00:00
TargetInstrInfo.h
Tail merging pass shall not break up IT blocks. rdar://8115404
2010-06-22 01:18:16 +00:00
TargetInstrItineraries.h
declare a class with 'class' instead of struct to avoid tag mismatch
2010-06-12 15:46:56 +00:00
TargetIntrinsicInfo.h
TargetJITInfo.h
TargetLowering.h
Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.
2010-06-23 17:09:26 +00:00
TargetLoweringObjectFile.h
Add a new section and accessor for TLS data.
2010-05-22 00:00:58 +00:00
TargetMachine.h
MC: Add TargetMachine support for setting the value of MCRelaxAll with
2010-05-26 21:48:55 +00:00
TargetOpcodes.h
- Fix description of SUBREG_TO_REG. It's not going to generate a zext. But it
2010-06-09 18:15:36 +00:00
TargetOptions.h
TargetRegisterInfo.h
Start TargetRegisterClass indices at 0 instead of 1, so that
2010-06-18 18:13:55 +00:00
TargetRegistry.h
Currently, createMachOStreamer() is invoked directly in llvm-mc which
2010-05-21 12:54:43 +00:00
TargetSchedule.td
TargetSelect.h
TargetSelectionDAG.td
finally remove the immAllOnesV_bc/immAllZerosV_bc patterns
2010-03-28 08:43:23 +00:00
TargetSelectionDAGInfo.h
TargetSubtarget.h