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Justin Holewinski
41085086b2
PTX: Fix predicate logic bug
Code such as: %vreg100 = setcc %vreg10, -1, SETNE brcond %vreg10, %tgt was being incorrectly morphed into %vreg100 = and %vreg10, 1 brcond %vreg10, %tgt where the 'and' instruction could be eliminated since such logic is on 1-bit types in the PTX back-end, leaving us with just: brcond %vreg10, %tgt which essentially gives us inverted branch conditions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153364 91177308-0d34-0410-b5e6-96231b3b80d8
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