Rafael Espindola 4a6855441c Change the default of AsmWriterClassName and isMCAsmWriter. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196065 91177308-0d34-0410-b5e6-96231b3b80d8

2013-12-02 04:55:42 +00:00

..

InstPrinter

[CMake] Let add_public_tablegen_target responsible to provide dependency to CommonTableGen.

2013-11-28 17:04:04 +00:00

MCTargetDesc

[CMake] Let add_public_tablegen_target responsible to provide dependency to CommonTableGen.

2013-11-28 17:04:04 +00:00

TargetInfo

[CMake] Let add_public_tablegen_target() provide intrinsics_gen, too.

2013-11-28 17:04:31 +00:00

AMDGPU.h

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AMDGPU.td

Change the default of AsmWriterClassName and isMCAsmWriter.

2013-12-02 04:55:42 +00:00

AMDGPUAsmPrinter.cpp

Indentation fixes

2013-11-14 10:08:50 +00:00

AMDGPUAsmPrinter.h

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AMDGPUCallingConv.td

R600: Use function inputs to represent data stored in gpr

2013-11-11 22:10:24 +00:00

AMDGPUConvertToISA.cpp

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AMDGPUFrameLowering.cpp

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AMDGPUFrameLowering.h

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AMDGPUInstrInfo.cpp

[weak vtables] Remove a bunch of weak vtables

2013-11-19 00:57:56 +00:00

AMDGPUInstrInfo.h

R600/SI: Implement spilling of SGPRs v5

2013-11-27 21:23:35 +00:00

AMDGPUInstrInfo.td

R600: Add support for ISD::FROUND

2013-11-27 21:23:20 +00:00

AMDGPUInstructions.td

R600/SI: Fixing handling of condition codes

2013-11-22 23:07:58 +00:00

AMDGPUIntrinsics.td

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AMDGPUISelDAGToDAG.cpp

R600/SI: Add support for private address space load/store

2013-11-13 23:36:50 +00:00

AMDGPUISelLowering.cpp

R600: Expand vector FABS

2013-11-27 21:23:39 +00:00

AMDGPUISelLowering.h

Add target hook to prevent folding some bitcasted loads.

2013-11-15 04:42:23 +00:00

AMDGPUMachineFunction.cpp

[weak vtables] Remove a bunch of weak vtables

2013-11-19 00:57:56 +00:00

AMDGPUMachineFunction.h

[weak vtables] Remove a bunch of weak vtables

2013-11-19 00:57:56 +00:00

AMDGPUMCInstLower.cpp

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AMDGPUMCInstLower.h

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AMDGPURegisterInfo.cpp

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AMDGPURegisterInfo.h

R600/SI: Add support for private address space load/store

2013-11-13 23:36:50 +00:00

AMDGPURegisterInfo.td

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AMDGPUSubtarget.cpp

R600: Enable the IR structurizer by default

2013-11-18 19:43:44 +00:00

AMDGPUSubtarget.h

R600: Add a SubtargetFeatture for disabling the ifcvt pass.

2013-11-18 19:43:33 +00:00

AMDGPUTargetMachine.cpp

R600: Enable the IR structurizer by default

2013-11-18 19:43:44 +00:00

AMDGPUTargetMachine.h

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AMDGPUTargetTransformInfo.cpp

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AMDILBase.td

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AMDILCFGStructurizer.cpp

R600: Fix a crash in the AMDILCFGStrucurizer

2013-11-18 19:43:38 +00:00

AMDILInstrInfo.td

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AMDILIntrinsicInfo.cpp

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AMDILIntrinsicInfo.h

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AMDILIntrinsics.td

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AMDILISelLowering.cpp

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AMDILRegisterInfo.td

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CMakeLists.txt

[CMake] Let add_public_tablegen_target() provide intrinsics_gen, too.

2013-11-28 17:04:31 +00:00

LLVMBuild.txt

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Makefile

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Processors.td

R600/SI: Add processor type for Hawaii

2013-11-14 23:46:00 +00:00

R600ClauseMergePass.cpp

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R600ControlFlowFinalizer.cpp

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R600Defines.h

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R600EmitClauseMarkers.cpp

R600: Fix scheduling of instructions that use the LDS output queue

2013-11-15 00:12:45 +00:00

R600ExpandSpecialInstrs.cpp

R600: Fix scheduling of instructions that use the LDS output queue

2013-11-15 00:12:45 +00:00

R600InstrFormats.td

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R600InstrInfo.cpp

R600: Implement TargetInstrInfo::isLegalToSplitMBBAt()

2013-11-22 00:41:08 +00:00

R600InstrInfo.h

R600: Implement TargetInstrInfo::isLegalToSplitMBBAt()

2013-11-22 00:41:08 +00:00

R600Instructions.td

R600: Add support for ISD::FROUND

2013-11-27 21:23:20 +00:00

R600Intrinsics.td

R600: Reenable llvm.R600.load.input/interp.input for compatibility

2013-11-12 16:26:47 +00:00

R600ISelLowering.cpp

R600: Fix scheduling of instructions that use the LDS output queue

2013-11-15 00:12:45 +00:00

R600ISelLowering.h

R600/SI: Add support for private address space load/store

2013-11-13 23:36:50 +00:00

R600MachineFunctionInfo.cpp

[weak vtables] Remove a bunch of weak vtables

2013-11-19 00:57:56 +00:00

R600MachineFunctionInfo.h

[weak vtables] Remove a bunch of weak vtables

2013-11-19 00:57:56 +00:00

R600MachineScheduler.cpp

R600: Fix scheduling of instructions that use the LDS output queue

2013-11-15 00:12:45 +00:00

R600MachineScheduler.h

R600: Fix scheduling of instructions that use the LDS output queue

2013-11-15 00:12:45 +00:00

R600OptimizeVectorRegisters.cpp

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R600Packetizer.cpp

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R600RegisterInfo.cpp

R600: Fix scheduling of instructions that use the LDS output queue

2013-11-15 00:12:45 +00:00

R600RegisterInfo.h

R600: Fix scheduling of instructions that use the LDS output queue

2013-11-15 00:12:45 +00:00

R600RegisterInfo.td

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R600Schedule.td

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R600TextureIntrinsicsReplacer.cpp

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SIAnnotateControlFlow.cpp

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SIDefines.h

R600/SI: Prefer SALU instructions for bit shift operations

2013-11-13 23:36:37 +00:00

SIFixSGPRCopies.cpp

R600/SI: Fix illegal VGPR->SGPR copy inside of loop

2013-11-18 18:50:20 +00:00

SIInsertWaits.cpp

R600/SI: Add support for private address space load/store

2013-11-13 23:36:50 +00:00

SIInstrFormats.td

R600/SI: Prefer SALU instructions for bit shift operations

2013-11-13 23:36:37 +00:00

SIInstrInfo.cpp

R600/SI: Implement spilling of SGPRs v5

2013-11-27 21:23:35 +00:00

SIInstrInfo.h

R600/SI: Implement spilling of SGPRs v5

2013-11-27 21:23:35 +00:00

SIInstrInfo.td

R600/SI: Add support for private address space load/store

2013-11-13 23:36:50 +00:00

SIInstructions.td

R600/SI: Implement spilling of SGPRs v5

2013-11-27 21:23:35 +00:00

SIIntrinsics.td

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SIISelLowering.cpp

R600/SI: Fixing handling of condition codes

2013-11-22 23:07:58 +00:00

SIISelLowering.h

R600/SI: Implement add i64, but do not yet enable.

2013-11-18 20:09:47 +00:00

SILowerControlFlow.cpp

R600/SI: Add support for private address space load/store

2013-11-13 23:36:50 +00:00

SIMachineFunctionInfo.cpp

R600/SI: Implement spilling of SGPRs v5

2013-11-27 21:23:35 +00:00

SIMachineFunctionInfo.h

R600/SI: Implement spilling of SGPRs v5

2013-11-27 21:23:35 +00:00

SIRegisterInfo.cpp

R600/SI: Fix moveToVALU when the first operand is VSrc.

2013-11-18 20:09:55 +00:00

SIRegisterInfo.h

R600/SI: Add support for private address space load/store

2013-11-13 23:36:50 +00:00

SIRegisterInfo.td

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SISchedule.td

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SITypeRewriter.cpp

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