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https://github.com/c64scene-ar/llvm-6502.git
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b8d7733666
Scalar integers are commuted to move constants to the RHS for re-association - this ensures vectors do the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234092 91177308-0d34-0410-b5e6-96231b3b80d8
120 lines
3.9 KiB
LLVM
120 lines
3.9 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s
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define <4 x i32> @add_4i32(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @add_4i32
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;CHECK: # BB#0:
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;CHECK-NEXT: paddd %xmm1, %xmm0
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;CHECK-NEXT: retq
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%1 = add <4 x i32> %a0, <i32 1, i32 -2, i32 3, i32 -4>
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%2 = add <4 x i32> %a1, <i32 -1, i32 2, i32 -3, i32 4>
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%3 = add <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @add_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @add_4i32_commute
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;CHECK: # BB#0:
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;CHECK-NEXT: paddd %xmm1, %xmm0
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;CHECK-NEXT: retq
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%1 = add <4 x i32> <i32 1, i32 -2, i32 3, i32 -4>, %a0
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%2 = add <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, %a1
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%3 = add <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @mul_4i32(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @mul_4i32
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;CHECK: # BB#0:
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;CHECK-NEXT: pmulld %xmm1, %xmm0
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;CHECK-NEXT: pmulld .LCPI2_0(%rip), %xmm0
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;CHECK-NEXT: retq
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%1 = mul <4 x i32> %a0, <i32 1, i32 2, i32 3, i32 4>
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%2 = mul <4 x i32> %a1, <i32 4, i32 3, i32 2, i32 1>
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%3 = mul <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @mul_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @mul_4i32_commute
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;CHECK: # BB#0:
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;CHECK-NEXT: pmulld %xmm1, %xmm0
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;CHECK-NEXT: pmulld .LCPI3_0(%rip), %xmm0
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;CHECK-NEXT: retq
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%1 = mul <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %a0
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%2 = mul <4 x i32> <i32 4, i32 3, i32 2, i32 1>, %a1
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%3 = mul <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @and_4i32(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @and_4i32
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;CHECK: # BB#0:
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;CHECK-NEXT: andps %xmm1, %xmm0
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;CHECK-NEXT: andps .LCPI4_0(%rip), %xmm0
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;CHECK-NEXT: retq
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%1 = and <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
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%2 = and <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
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%3 = and <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @and_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @and_4i32_commute
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;CHECK: # BB#0:
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;CHECK-NEXT: andps %xmm1, %xmm0
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;CHECK-NEXT: andps .LCPI5_0(%rip), %xmm0
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;CHECK-NEXT: retq
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%1 = and <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
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%2 = and <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
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%3 = and <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @or_4i32(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @or_4i32
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;CHECK: # BB#0:
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;CHECK-NEXT: orps %xmm1, %xmm0
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;CHECK-NEXT: orps .LCPI6_0(%rip), %xmm0
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;CHECK-NEXT: retq
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%1 = or <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
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%2 = or <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
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%3 = or <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @or_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @or_4i32_commute
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;CHECK: # BB#0:
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;CHECK-NEXT: orps %xmm1, %xmm0
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;CHECK-NEXT: orps .LCPI7_0(%rip), %xmm0
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;CHECK-NEXT: retq
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%1 = or <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
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%2 = or <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
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%3 = or <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @xor_4i32(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @xor_4i32
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;CHECK: # BB#0:
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;CHECK-NEXT: xorps %xmm1, %xmm0
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;CHECK-NEXT: xorps .LCPI8_0(%rip), %xmm0
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;CHECK-NEXT: retq
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%1 = xor <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
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%2 = xor <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
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%3 = xor <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @xor_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
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;CHECK-LABEL: @xor_4i32_commute
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;CHECK: # BB#0:
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;CHECK-NEXT: xorps %xmm1, %xmm0
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;CHECK-NEXT: xorps .LCPI9_0(%rip), %xmm0
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;CHECK-NEXT: retq
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%1 = xor <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
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%2 = xor <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
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%3 = xor <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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