Jiangning Liu 082ac99cc8 Implement AArch64 NEON instruction set AdvSIMD (table). ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8

2013-11-14 01:57:32 +00:00

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AArch64

Implement AArch64 NEON instruction set AdvSIMD (table).

2013-11-14 01:57:32 +00:00

ARM

[ARM] Add support for MVFR2 which is new in ARMv8

2013-11-11 19:56:13 +00:00

Mips

Support for microMIPS trap instruction with immediate operands.

2013-11-13 13:15:03 +00:00

SystemZ

[SystemZ] Add the general form of BCR

2013-11-13 16:57:53 +00:00

X86

Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.

2013-10-14 01:42:32 +00:00

XCore

[tests] Cleanup initialization of test suffixes.

2013-08-16 00:37:11 +00:00