This website requires JavaScript.
Explore
Mirrors
Help
Sign In
6502
/
llvm-6502
Watch
1
Star
0
Fork
0
You've already forked llvm-6502
mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced
2025-01-25 00:33:15 +00:00
Code
Issues
Projects
Releases
Wiki
Activity
llvm-6502
/
test
/
MC
/
Disassembler
History
Colin LeMahieu
cf2daa3671
[Hexagon] Adding combine reg, reg with predicated forms.
...
git-svn-id:
https://llvm.org/svn/llvm-project/llvm/trunk@223667
91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-08 17:33:06 +00:00
..
AArch64
…
ARM
Add support for ARM modified-immediate assembly syntax.
2014-12-02 10:53:20 +00:00
Hexagon
[Hexagon] Adding combine reg, reg with predicated forms.
2014-12-08 17:33:06 +00:00
Mips
The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.
2014-12-01 11:12:04 +00:00
PowerPC
…
Sparc
…
SystemZ
…
X86
…
XCore
…
