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f98f2ce29e
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
125 lines
3.4 KiB
C++
125 lines
3.4 KiB
C++
//===-- AMDILDevice.cpp - Base class for AMDIL Devices --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//==-----------------------------------------------------------------------===//
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#include "AMDILDevice.h"
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#include "AMDGPUSubtarget.h"
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using namespace llvm;
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// Default implementation for all of the classes.
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AMDGPUDevice::AMDGPUDevice(AMDGPUSubtarget *ST) : mSTM(ST) {
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mHWBits.resize(AMDGPUDeviceInfo::MaxNumberCapabilities);
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mSWBits.resize(AMDGPUDeviceInfo::MaxNumberCapabilities);
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setCaps();
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DeviceFlag = OCL_DEVICE_ALL;
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}
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AMDGPUDevice::~AMDGPUDevice() {
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mHWBits.clear();
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mSWBits.clear();
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}
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size_t AMDGPUDevice::getMaxGDSSize() const {
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return 0;
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}
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uint32_t
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AMDGPUDevice::getDeviceFlag() const {
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return DeviceFlag;
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}
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size_t AMDGPUDevice::getMaxNumCBs() const {
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if (usesHardware(AMDGPUDeviceInfo::ConstantMem)) {
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return HW_MAX_NUM_CB;
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}
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return 0;
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}
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size_t AMDGPUDevice::getMaxCBSize() const {
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if (usesHardware(AMDGPUDeviceInfo::ConstantMem)) {
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return MAX_CB_SIZE;
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}
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return 0;
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}
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size_t AMDGPUDevice::getMaxScratchSize() const {
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return 65536;
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}
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uint32_t AMDGPUDevice::getStackAlignment() const {
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return 16;
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}
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void AMDGPUDevice::setCaps() {
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mSWBits.set(AMDGPUDeviceInfo::HalfOps);
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mSWBits.set(AMDGPUDeviceInfo::ByteOps);
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mSWBits.set(AMDGPUDeviceInfo::ShortOps);
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mSWBits.set(AMDGPUDeviceInfo::HW64BitDivMod);
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if (mSTM->isOverride(AMDGPUDeviceInfo::NoInline)) {
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mSWBits.set(AMDGPUDeviceInfo::NoInline);
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}
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if (mSTM->isOverride(AMDGPUDeviceInfo::MacroDB)) {
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mSWBits.set(AMDGPUDeviceInfo::MacroDB);
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}
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if (mSTM->isOverride(AMDGPUDeviceInfo::Debug)) {
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mSWBits.set(AMDGPUDeviceInfo::ConstantMem);
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} else {
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mHWBits.set(AMDGPUDeviceInfo::ConstantMem);
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}
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if (mSTM->isOverride(AMDGPUDeviceInfo::Debug)) {
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mSWBits.set(AMDGPUDeviceInfo::PrivateMem);
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} else {
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mHWBits.set(AMDGPUDeviceInfo::PrivateMem);
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}
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if (mSTM->isOverride(AMDGPUDeviceInfo::BarrierDetect)) {
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mSWBits.set(AMDGPUDeviceInfo::BarrierDetect);
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}
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mSWBits.set(AMDGPUDeviceInfo::ByteLDSOps);
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mSWBits.set(AMDGPUDeviceInfo::LongOps);
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}
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AMDGPUDeviceInfo::ExecutionMode
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AMDGPUDevice::getExecutionMode(AMDGPUDeviceInfo::Caps Caps) const {
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if (mHWBits[Caps]) {
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assert(!mSWBits[Caps] && "Cannot set both SW and HW caps");
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return AMDGPUDeviceInfo::Hardware;
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}
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if (mSWBits[Caps]) {
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assert(!mHWBits[Caps] && "Cannot set both SW and HW caps");
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return AMDGPUDeviceInfo::Software;
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}
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return AMDGPUDeviceInfo::Unsupported;
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}
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bool AMDGPUDevice::isSupported(AMDGPUDeviceInfo::Caps Mode) const {
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return getExecutionMode(Mode) != AMDGPUDeviceInfo::Unsupported;
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}
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bool AMDGPUDevice::usesHardware(AMDGPUDeviceInfo::Caps Mode) const {
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return getExecutionMode(Mode) == AMDGPUDeviceInfo::Hardware;
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}
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bool AMDGPUDevice::usesSoftware(AMDGPUDeviceInfo::Caps Mode) const {
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return getExecutionMode(Mode) == AMDGPUDeviceInfo::Software;
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}
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std::string
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AMDGPUDevice::getDataLayout() const {
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return std::string("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16"
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"-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32"
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"-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64"
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"-v96:128:128-v128:128:128-v192:256:256-v256:256:256"
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"-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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"-n8:16:32:64");
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}
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