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4397294e78
This function is going to be removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170064 91177308-0d34-0410-b5e6-96231b3b80d8
109 lines
3.5 KiB
C++
109 lines
3.5 KiB
C++
//===-- SILowerLiteralConstants.cpp - Lower intrs using literal constants--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief This pass performs the following transformation on instructions with
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/// literal constants:
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///
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/// %VGPR0 = V_MOV_IMM_I32 1
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///
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/// becomes:
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///
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/// BUNDLE
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/// * %VGPR = V_MOV_B32_32 SI_LITERAL_CONSTANT
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/// * SI_LOAD_LITERAL 1
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///
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/// The resulting sequence matches exactly how the hardware handles immediate
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/// operands, so this transformation greatly simplifies the code generator.
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///
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/// Only the *_MOV_IMM_* support immediate operands at the moment, but when
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/// support for immediate operands is added to other instructions, they
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/// will be lowered here as well.
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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using namespace llvm;
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namespace {
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class SILowerLiteralConstantsPass : public MachineFunctionPass {
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private:
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static char ID;
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const TargetInstrInfo *TII;
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public:
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SILowerLiteralConstantsPass(TargetMachine &tm) :
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MachineFunctionPass(ID), TII(tm.getInstrInfo()) { }
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virtual bool runOnMachineFunction(MachineFunction &MF);
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const char *getPassName() const {
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return "SI Lower literal constants pass";
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}
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};
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} // End anonymous namespace
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char SILowerLiteralConstantsPass::ID = 0;
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FunctionPass *llvm::createSILowerLiteralConstantsPass(TargetMachine &tm) {
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return new SILowerLiteralConstantsPass(tm);
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}
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bool SILowerLiteralConstantsPass::runOnMachineFunction(MachineFunction &MF) {
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for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
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BB != BB_E; ++BB) {
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MachineBasicBlock &MBB = *BB;
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for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
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I != MBB.end(); I = Next) {
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Next = llvm::next(I);
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MachineInstr &MI = *I;
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switch (MI.getOpcode()) {
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default: break;
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case AMDGPU::S_MOV_IMM_I32:
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case AMDGPU::S_MOV_IMM_I64:
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case AMDGPU::V_MOV_IMM_F32:
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case AMDGPU::V_MOV_IMM_I32: {
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unsigned MovOpcode;
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unsigned LoadLiteralOpcode;
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MachineOperand LiteralOp = MI.getOperand(1);
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if (AMDGPU::VReg_32RegClass.contains(MI.getOperand(0).getReg())) {
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MovOpcode = AMDGPU::V_MOV_B32_e32;
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} else {
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MovOpcode = AMDGPU::S_MOV_B32;
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}
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if (LiteralOp.isImm()) {
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LoadLiteralOpcode = AMDGPU::SI_LOAD_LITERAL_I32;
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} else {
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LoadLiteralOpcode = AMDGPU::SI_LOAD_LITERAL_F32;
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}
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MIBundleBuilder Bundle(MBB, I);
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Bundle
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.append(BuildMI(MF, MBB.findDebugLoc(I), TII->get(MovOpcode),
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MI.getOperand(0).getReg())
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.addReg(AMDGPU::SI_LITERAL_CONSTANT))
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.append(BuildMI(MF, MBB.findDebugLoc(I),
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TII->get(LoadLiteralOpcode))
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.addOperand(MI.getOperand(1)));
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llvm::finalizeBundle(MBB, Bundle.begin());
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MI.eraseFromParent();
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break;
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}
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}
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}
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}
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return false;
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}
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