Matheus Almeida 45ecbfc8e5 [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction. ...

INSERT is the first type of MSA instruction that requires a change to the way
MSA registers are parsed. This happens because MSA registers may be suffixed by
an index in the form of an immediate or a general purpose register. The changes
to parseMSARegs reflect that requirement.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192582 91177308-0d34-0410-b5e6-96231b3b80d8

2013-10-14 11:49:30 +00:00

..

AArch64

Implement aarch64 neon instruction set AdvSIMD (copy).

2013-10-11 02:33:55 +00:00

ARM

[ARM] Fix FP ABI attributes with no VFP enabled.

2013-10-11 16:03:43 +00:00

AsmParser

MCParser/Debug info: Accept line number 0 as a legitimate value, since

2013-09-26 23:37:11 +00:00

COFF

…

Disassembler

Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.

2013-10-14 01:42:32 +00:00

ELF

Implements parsing and emitting of .cfi_window_save in MC.

2013-09-26 14:49:40 +00:00

MachO

Add test I forgot to git add in r191824.

2013-10-02 14:49:41 +00:00

Markup

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Mips

[mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.

2013-10-14 11:49:30 +00:00

PowerPC

PPC: Allow partial fills in writeNopData()

2013-09-26 09:18:48 +00:00

SystemZ

[SystemZ] Add comparisons of high words and memory

2013-10-01 15:00:44 +00:00

X86

Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.

2013-10-14 04:55:01 +00:00