Tim Northover c4cc006a09 AArch64: remove accidental test output file. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184236 91177308-0d34-0410-b5e6-96231b3b80d8

2013-06-18 21:16:53 +00:00

..

AArch64

AArch64: remove accidental test output file.

2013-06-18 21:16:53 +00:00

ARM

During SelectionDAG building explicitly set a node to constant zero when the

2013-06-18 20:14:39 +00:00

CPP

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Generic

Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.

2013-05-21 14:37:16 +00:00

Hexagon

Hexagon: Pass to replace tranfer/copy instructions into combine instruction

2013-05-14 18:54:06 +00:00

Inputs

Revert "Adding DIImportedModules to DIScopes."

2013-03-28 02:44:59 +00:00

MBlaze

Remove unnecessary leading comment characters in lit-only file

2013-03-18 22:08:16 +00:00

Mips

[mips] Add an IR transformation pass that optimizes calls to sqrt.

2013-06-11 22:21:44 +00:00

MSP430

DAGCombiner: Simplify inverted bit tests

2013-05-08 06:44:42 +00:00

NVPTX

[NVPTX] Remove old CONST_NOT_GEN address space that is not being used anymore and causes constants to be emitted in the global address space

2013-06-10 13:29:47 +00:00

PowerPC

[PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.

2013-06-13 20:23:34 +00:00

R600

R600: PV stores Reg id, not index

2013-06-17 20:16:40 +00:00

SI

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SPARC

Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.

2013-06-17 19:00:36 +00:00

SystemZ

[SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses

2013-05-31 13:25:22 +00:00

Thumb

LocalStackSlotAllocation improvements

2013-04-30 20:04:37 +00:00

Thumb2

Cortex-R5 can issue Thumb2 integer division instructions.

2013-06-04 22:52:09 +00:00

X86

During SelectionDAG building explicitly set a node to constant zero when the

2013-06-18 20:14:39 +00:00

XCore

[XCore] Fix handling of functions where only the LR is spilled.

2013-05-09 16:43:42 +00:00