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https://github.com/c64scene-ar/llvm-6502.git
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de3aa4f77f
(non-working) of llc guts for X86, and add a prototype for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6779 91177308-0d34-0410-b5e6-96231b3b80d8
100 lines
3.2 KiB
C++
100 lines
3.2 KiB
C++
//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
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//
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// This file defines the X86 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#include "X86TargetMachine.h"
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#include "X86.h"
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#include "llvm/PassManager.h"
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#include "llvm/Target/TargetMachineImpls.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Transforms/Scalar.h"
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#include "Support/CommandLine.h"
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#include "Support/Statistic.h"
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#include <iostream>
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namespace {
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cl::opt<bool> NoLocalRA("disable-local-ra",
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cl::desc("Use Simple RA instead of Local RegAlloc"));
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cl::opt<bool> PrintCode("print-machineinstrs",
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cl::desc("Print generated machine code"));
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}
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// allocateX86TargetMachine - Allocate and return a subclass of TargetMachine
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// that implements the X86 backend.
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//
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TargetMachine *allocateX86TargetMachine(unsigned Configuration) {
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return new X86TargetMachine(Configuration);
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}
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/// X86TargetMachine ctor - Create an ILP32 architecture model
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///
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X86TargetMachine::X86TargetMachine(unsigned Config)
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: TargetMachine("X86",
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(Config & TM::EndianMask) == TM::LittleEndian,
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(Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4,
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(Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4,
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(Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4),
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FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, 4) {
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}
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// llc backend for x86
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bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
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std::ostream &Out) {
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PM.add(createLowerSwitchPass());
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PM.add(createSimpleX86InstructionSelector(*this));
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PM.add(createLocalRegisterAllocator());
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PM.add(createX86FloatingPointStackifierPass());
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PM.add(createPrologEpilogCodeInserter());
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PM.add(createX86PeepholeOptimizerPass());
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PM.add(createX86CodePrinterPass(Out));
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return false; // success!
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}
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/// addPassesToJITCompile - Add passes to the specified pass manager to
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/// implement a fast dynamic compiler for this target. Return true if this is
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/// not supported for this target.
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///
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bool X86TargetMachine::addPassesToJITCompile(PassManager &PM) {
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// FIXME: Implement the switch instruction in the instruction selector!
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PM.add(createLowerSwitchPass());
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PM.add(createSimpleX86InstructionSelector(*this));
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// TODO: optional optimizations go here
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// FIXME: Add SSA based peephole optimizer here.
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// Print the instruction selected machine code...
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if (PrintCode)
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PM.add(createMachineFunctionPrinterPass());
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// Perform register allocation to convert to a concrete x86 representation
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if (NoLocalRA)
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PM.add(createSimpleRegisterAllocator());
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else
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PM.add(createLocalRegisterAllocator());
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if (PrintCode)
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PM.add(createMachineFunctionPrinterPass());
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PM.add(createX86FloatingPointStackifierPass());
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if (PrintCode)
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PM.add(createMachineFunctionPrinterPass());
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// Insert prolog/epilog code. Eliminate abstract frame index references...
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PM.add(createPrologEpilogCodeInserter());
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PM.add(createX86PeepholeOptimizerPass());
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if (PrintCode) // Print the register-allocated code
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PM.add(createX86CodePrinterPass(std::cerr));
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return false; // success!
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}
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