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======================
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LLVM 3.3 Release Notes
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======================
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.. contents::
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:local:
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.. warning::
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These are in-progress notes for the upcoming LLVM 3.3 release. You may
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prefer the `LLVM 3.2 Release Notes <http://llvm.org/releases/3.2/docs
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/ReleaseNotes.html>`_.
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Introduction
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============
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This document contains the release notes for the LLVM Compiler Infrastructure,
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release 3.3. Here we describe the status of LLVM, including major improvements
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from the previous release, improvements in various subprojects of LLVM, and
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some of the current users of the code. All LLVM releases may be downloaded
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from the `LLVM releases web site <http://llvm.org/releases/>`_.
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For more information about LLVM, including information about the latest
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release, please check out the `main LLVM web site <http://llvm.org/>`_. If you
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have questions or comments, the `LLVM Developer's Mailing List
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<http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev>`_ is a good place to send
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them.
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Note that if you are reading this file from a Subversion checkout or the main
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LLVM web page, this document applies to the *next* release, not the current
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one. To see the release notes for a specific release, please see the `releases
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page <http://llvm.org/releases/>`_.
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Non-comprehensive list of changes in this release
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=================================================
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.. NOTE
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For small 1-3 sentence descriptions, just add an entry at the end of
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this list. If your description won't fit comfortably in one bullet
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point (e.g. maybe you would like to give an example of the
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functionality, or simply have a lot to talk about), see the `NOTE` below
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for adding a new subsection.
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* The CellSPU port has been removed. It can still be found in older versions.
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* The IR-level extended linker APIs (for example, to link bitcode files out of
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archives) have been removed. Any existing clients of these features should
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move to using a linker with integrated LTO support.
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* LLVM and Clang's documentation has been migrated to the `Sphinx
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<http://sphinx-doc.org/>`_ documentation generation system which uses
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easy-to-write reStructuredText. See `llvm/docs/README.txt` for more
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information.
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* TargetTransformInfo (TTI) is a new interface that can be used by IR-level
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passes to obtain target-specific information, such as the costs of
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instructions. Only "Lowering" passes such as LSR and the vectorizer are
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allowed to use the TTI infrastructure.
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* We've improved the X86 and ARM cost model.
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* The Attributes classes have been completely rewritten and expanded. They now
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support not only enumerated attributes and alignments, but "string"
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attributes, which are useful for passing information to code generation. See
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:doc:`HowToUseAttributes` for more details.
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* TableGen's syntax for instruction selection patterns has been simplified.
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Instead of specifying types indirectly with register classes, you should now
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specify types directly in the input patterns. See ``SparcInstrInfo.td`` for
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examples of the new syntax. The old syntax using register classes still
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works, but it will be removed in a future LLVM release.
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* MCJIT now supports exception handling. Support for it in the old jit will be
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removed in the 3.4 release.
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* ... next change ...
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.. NOTE
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If you would like to document a larger change, then you can add a
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subsection about it right here. You can copy the following boilerplate
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and un-indent it (the indentation causes it to be inside this comment).
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Special New Feature
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-------------------
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Makes programs 10x faster by doing Special New Thing.
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AArch64 target
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--------------
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We've added support for AArch64, ARM's 64-bit architecture. Development is still
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in fairly early stages, but we expect successful compilation when:
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- compiling standard compliant C99 and C++03 with Clang;
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- using Linux as a target platform;
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- where code + static data doesn't exceed 4GB in size (heap allocated data has
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no limitation).
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Some additional functionality is also implemented, notably DWARF debugging,
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GNU-style thread local storage and inline assembly.
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Hexagon Target
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--------------
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- Removed support for legacy hexagonv2 and hexagonv3 processor
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architectures which are no longer in use. Currently supported
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architectures are hexagonv4 and hexagonv5.
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Loop Vectorizer
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---------------
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We've continued the work on the loop vectorizer. The loop vectorizer now
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has the following features:
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- Loops with unknown trip counts.
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- Runtime checks of pointers.
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- Reductions, Inductions.
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- Min/Max reductions of integers.
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- If Conversion.
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- Pointer induction variables.
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- Reverse iterators.
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- Vectorization of mixed types.
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- Vectorization of function calls.
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- Partial unrolling during vectorization.
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The loop vectorizer is now enabled by default for -O3.
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SLP Vectorizer
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--------------
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LLVM now has a new SLP vectorizer. The new SLP vectorizer is not enabled by
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default but can be enabled using the clang flag -fslp-vectorize. The BB-vectorizer
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can also be enabled using the command line flag -fslp-vectorize-aggressive.
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R600 Backend
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------------
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The R600 backend was added in this release, it supports AMD GPUs
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(HD2XXX - HD7XXX). This backend is used in AMD's Open Source
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graphics / compute drivers which are developed as part of the `Mesa3D
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<http://www.mesa3d.org>`_ project.
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SystemZ/s390x Backend
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---------------------
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LLVM and clang now support IBM's z/Architecture. At present this support
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is restricted to GNU/Linux (GNU triplet s390x-linux-gnu) and requires
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z10 or greater.
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External Open Source Projects Using LLVM 3.3
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============================================
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An exciting aspect of LLVM is that it is used as an enabling technology for
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a lot of other language and tools projects. This section lists some of the
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projects that have already been updated to work with LLVM 3.3.
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Portable Computing Language (pocl)
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----------------------------------
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In addition to producing an easily portable open source OpenCL
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implementation, another major goal of `pocl <http://pocl.sourceforge.net/>`_
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is improving performance portability of OpenCL programs with
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compiler optimizations, reducing the need for target-dependent manual
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optimizations. An important part of pocl is a set of LLVM passes used to
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statically parallelize multiple work-items with the kernel compiler, even in
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the presence of work-group barriers. This enables static parallelization of
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the fine-grained static concurrency in the work groups in multiple ways.
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TTA-based Co-design Environment (TCE)
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-------------------------------------
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`TCE <http://tce.cs.tut.fi/>`_ is a toolset for designing new
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processors based on the Transport triggered architecture (TTA).
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The toolset provides a complete co-design flow from C/C++
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programs down to synthesizable VHDL/Verilog and parallel program binaries.
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Processor customization points include the register files, function units,
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supported operations, and the interconnection network.
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TCE uses Clang and LLVM for C/C++/OpenCL C language support, target independent
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optimizations and also for parts of code generation. It generates new
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LLVM-based code generators "on the fly" for the designed TTA processors and
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loads them in to the compiler backend as runtime libraries to avoid
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per-target recompilation of larger parts of the compiler chain.
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Additional Information
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======================
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A wide variety of additional information is available on the `LLVM web page
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<http://llvm.org/>`_, in particular in the `documentation
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<http://llvm.org/docs/>`_ section. The web page also contains versions of the
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API documentation which is up-to-date with the Subversion version of the source
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code. You can access versions of these documents specific to this release by
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going into the ``llvm/docs/`` directory in the LLVM tree.
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If you have any questions or comments about LLVM, please feel free to contact
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us via the `mailing lists <http://llvm.org/docs/#maillist>`_.
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