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630c5e06d6
Previously we modelled VPR128 and VPR64 as essentially identical register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias" sub-registers). This model is starting to cause significant problems for code generation, particularly writing EXTRACT/INSERT_SUBREG patterns for converting between the two. The change here switches to classifying VPR64 & VPR128 as RegisterOperands, which are essentially aliases for RegisterClasses with different parsing and printing behaviour. This fits almost exactly with their real status (VPR128 == FPR128 printed strangely, VPR64 == FPR64 printed strangely). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190665 91177308-0d34-0410-b5e6-96231b3b80d8 |
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| .. | ||
| basic-a64-diagnostics.s | ||
| basic-a64-instructions.s | ||
| elf-globaladdress.ll | ||
| elf-objdump.s | ||
| elf-reloc-addend.s | ||
| elf-reloc-addsubimm.s | ||
| elf-reloc-condbr.s | ||
| elf-reloc-ldrlit.s | ||
| elf-reloc-ldstunsimm.s | ||
| elf-reloc-movw.s | ||
| elf-reloc-pcreladdressing.s | ||
| elf-reloc-tstb.s | ||
| elf-reloc-uncondbrimm.s | ||
| gicv3-regs-diagnostics.s | ||
| gicv3-regs.s | ||
| lit.local.cfg | ||
| mapping-across-sections.s | ||
| mapping-within-section.s | ||
| neon-3vdiff.s | ||
| neon-aba-abd.s | ||
| neon-add-pairwise.s | ||
| neon-add-sub-instructions.s | ||
| neon-bitwise-instructions.s | ||
| neon-compare-instructions.s | ||
| neon-diagnostics.s | ||
| neon-facge-facgt.s | ||
| neon-frsqrt-frecp.s | ||
| neon-halving-add-sub.s | ||
| neon-max-min-pairwise.s | ||
| neon-max-min.s | ||
| neon-mla-mls-instructions.s | ||
| neon-mov.s | ||
| neon-mul-div-instructions.s | ||
| neon-rounding-halving-add.s | ||
| neon-rounding-shift.s | ||
| neon-saturating-add-sub.s | ||
| neon-saturating-rounding-shift.s | ||
| neon-saturating-shift.s | ||
| neon-shift-left-long.s | ||
| neon-shift.s | ||
| neon-simd-shift.s | ||
| noneon-diagnostics.s | ||
| tls-relocs.s | ||
| trace-regs-diagnostics.s | ||
| trace-regs.s | ||