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llvm-6502/include/llvm/CodeGen
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Evan Cheng dbf67fefea Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 23:55:47 +00:00
..
Analysis.h
Move several SelectionDAG-independent utility functions out of the
2010-04-21 01:22:34 +00:00
AsmPrinter.h
Rework global alignment computation again. Now we do round up
2010-04-28 19:58:07 +00:00
BinaryObject.h
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CalcSpillWeights.h
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CallingConvLower.h
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FastISel.h
Add initial kill flag support to FastISel.
2010-05-11 23:54:07 +00:00
GCMetadata.h
Add const qualifiers to CodeGen's use of LLVM IR constructs.
2010-04-15 01:51:59 +00:00
GCMetadataPrinter.h
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GCs.h
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GCStrategy.h
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IntrinsicLowering.h
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ISDOpcodes.h
Elaborate on a comment.
2010-04-29 16:57:54 +00:00
JITCodeEmitter.h
Add a "PadTo" field to the emitULEB128Bytes method. This will pad out to the
2010-04-18 00:51:49 +00:00
LatencyPriorityQueue.h
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LinkAllAsmWriterComponents.h
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LinkAllCodegenComponents.h
Add fast register allocator, enabled with -regalloc=fast.
2010-04-21 18:02:42 +00:00
LiveInterval.h
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LiveIntervalAnalysis.h
Teach liveintervalanalysis about virtual registers which are defined by reg_sequence instructions that are formed by registers defined by distinct instructions. e.g.
2010-05-05 18:27:40 +00:00
LiveStackAnalysis.h
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LiveVariables.h
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MachineBasicBlock.h
Eliminate MachineBasicBlock::const_livein_iterator and make
2010-04-13 16:57:55 +00:00
MachineCodeEmitter.h
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MachineCodeInfo.h
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MachineConstantPool.h
Add const qualifiers to CodeGen's use of LLVM IR constructs.
2010-04-15 01:51:59 +00:00
MachineDominators.h
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MachineFrameInfo.h
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MachineFunction.h
Remove MachineFunction's DefaultDebugLoc member, and make DwarfDebug.cpp
2010-04-20 00:37:27 +00:00
MachineFunctionAnalysis.h
Give MachineModuleInfo an actual Module*.
2010-04-06 00:51:52 +00:00
MachineFunctionPass.h
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MachineInstr.h
Teach MachineLICM and MachineSink how to clear kill flags conservatively
2010-05-13 20:34:42 +00:00
MachineInstrBuilder.h
Add const qualifiers to CodeGen's use of LLVM IR constructs.
2010-04-15 01:51:59 +00:00
MachineJumpTableInfo.h
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MachineLocation.h
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MachineLoopInfo.h
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MachineMemOperand.h
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MachineModuleInfo.h
The JIT calls TidyLandingPads to tidy up the landing pads. However, because the
2010-04-16 08:46:10 +00:00
MachineModuleInfoImpls.h
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MachineOperand.h
Add const qualifiers to CodeGen's use of LLVM IR constructs.
2010-04-15 01:51:59 +00:00
MachinePassRegistry.h
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MachineRegisterInfo.h
Add a utility function for conservatively clearing kill flags, and make
2010-05-13 19:24:00 +00:00
MachineRelocation.h
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MachineSSAUpdater.h
Combine the implementations of the core part of the SSAUpdater and
2010-05-04 23:18:19 +00:00
MachORelocation.h
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ObjectCodeEmitter.h
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Passes.h
Add fast register allocator, enabled with -regalloc=fast.
2010-04-21 18:02:42 +00:00
ProcessImplicitDefs.h
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PseudoSourceValue.h
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RegAllocRegistry.h
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RegisterCoalescer.h
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RegisterScavenging.h
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RuntimeLibcalls.h
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ScheduleDAG.h
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
2010-05-01 00:01:06 +00:00
ScheduleHazardRecognizer.h
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SchedulerRegistry.h
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SelectionDAG.h
Implement a bunch more TargetSelectionDAGInfo infrastructure.
2010-05-11 17:31:57 +00:00
SelectionDAGISel.h
Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel
2010-04-22 20:46:50 +00:00
SelectionDAGNodes.h
Add const qualifiers to CodeGen's use of LLVM IR constructs.
2010-04-15 01:51:59 +00:00
SlotIndexes.h
remove some unneeded errorhandling stuff.
2010-04-07 22:44:07 +00:00
TargetLoweringObjectFileImpl.h
switch MCSectionCOFF from a syntactic to semantic representation,
2010-05-07 17:17:41 +00:00
ValueTypes.h
Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers.
2010-05-13 23:55:47 +00:00
ValueTypes.td
Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers.
2010-05-13 23:55:47 +00:00