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https://github.com/c64scene-ar/llvm-6502.git
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b5523ce1bb
These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8
37 lines
1.3 KiB
ArmAsm
37 lines
1.3 KiB
ArmAsm
@ New ARMv8 T32 encodings
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@ RUN: llvm-mc -triple thumbv8 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-V8
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@ RUN: not llvm-mc -triple thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
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@ HLT
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hlt #0
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hlt #63
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@ CHECK-V8: hlt #0 @ encoding: [0x80,0xba]
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@ CHECK-V8: hlt #63 @ encoding: [0xbf,0xba]
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@ CHECK-V7: error: instruction requires: armv8
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@ CHECK-V7: error: instruction requires: armv8
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@ In IT block
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it pl
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hlt #24
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@ CHECK-V8: it pl @ encoding: [0x58,0xbf]
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@ CHECK-V8: hlt #24 @ encoding: [0x98,0xba]
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@ CHECK-V7: error: instruction requires: armv8
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@ Can accept AL condition code
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hltal #24
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@ CHECK-V8: hlt #24 @ encoding: [0x98,0xba]
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@ CHECK-V7: error: instruction requires: armv8
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@ DCPS{1,2,3}
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dcps1
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dcps2
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dcps3
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@ CHECK-V8: dcps1 @ encoding: [0x8f,0xf7,0x01,0x80]
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@ CHECK-V8: dcps2 @ encoding: [0x8f,0xf7,0x02,0x80]
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@ CHECK-V8: dcps3 @ encoding: [0x8f,0xf7,0x03,0x80]
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@ CHECK-V7: error: instruction requires: armv8
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@ CHECK-V7: error: instruction requires: armv8
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@ CHECK-V7: error: instruction requires: armv8
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