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llvm-6502/test/MC/Disassembler/X86
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Ben Langmuir 1f1bd9a54d Partial support for Intel SHA Extensions (sha1rnds4) 
Add basic assembly/disassembly support for the first Intel SHA
instruction 'sha1rnds4'. Also includes feature flag, and test cases.

Support for the remaining instructions will follow in a separate patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-12 15:51:31 +00:00
..
hex-immediates.txt
intel-syntax-32.txt First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. 2013-08-25 22:23:38 +00:00
intel-syntax.txt First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. 2013-08-25 22:23:38 +00:00
invalid-cmp-imm.txt
invalid-VEX-vvvv.txt
lit.local.cfg
marked-up.txt
prefixes.txt Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode. 2013-08-30 21:19:48 +00:00
simple-tests.txt
truncated-input.txt
x86-32.txt First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. 2013-08-25 22:23:38 +00:00
x86-64.txt Partial support for Intel SHA Extensions (sha1rnds4) 2013-09-12 15:51:31 +00:00