Johnny Chen c3281c10c9 A7.3 register encoding ...

Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8

2011-04-05 22:57:07 +00:00

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Analysis

remove postdom frontiers, because it is dead. Forward dom frontiers are

2011-04-05 21:57:17 +00:00

Archive

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Assembler

Remove some support for ReturnInsts with multiple operands, and for

2011-04-04 07:44:02 +00:00

Bindings/Ocaml

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Bitcode

Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. Frontends

2011-03-29 23:06:19 +00:00

BugPoint

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CodeGen

These tests no longer require linear scan because reserved register coalescing is now universal.

2011-04-05 21:40:41 +00:00

DebugInfo

Move test in x86 specific area.

2011-03-24 22:39:09 +00:00

ExecutionEngine

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Feature

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FrontendAda

Will not compile without the spec!

2011-03-31 10:03:32 +00:00

FrontendC

Testcase for r128619 (PR9571).

2011-03-31 08:13:57 +00:00

FrontendC++

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FrontendFortran

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FrontendObjC

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FrontendObjC++

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Integer

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lib

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Linker

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LLVMC

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MC

A7.3 register encoding

2011-04-05 22:57:07 +00:00

Object

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Other

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Scripts

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TableGen

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Transforms

InstCombine optimizes gep(bitcast(x)) even when the bitcasts casts away address

2011-04-05 14:29:52 +00:00

Unit

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Verifier

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CMakeLists.txt

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lit.cfg

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lit.site.cfg.in

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Makefile

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Makefile.tests

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site.exp.in

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TestRunner.sh

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