llvm-6502/lib/Target/Sparc
Brian Gaeke 495a0974f4 Support cast float to float, cast double to float, and cast float to double.
(It's not yet clear how to copy doubles from register to register.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14371 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-24 21:22:08 +00:00
..
DelaySlotFiller.cpp JMPL has a delay slot. 2004-06-18 08:18:54 +00:00
InstSelectSimple.cpp Support cast float to float, cast double to float, and cast float to double. 2004-06-24 21:22:08 +00:00
Makefile
README.txt
Sparc.h
Sparc.td
SparcAsmPrinter.cpp Rename the load and store opcodes. The non-fp ones only have one 2004-06-24 07:37:12 +00:00
SparcInstrInfo.cpp
SparcInstrInfo.h
SparcInstrInfo.td Rename the load and store opcodes. The non-fp ones only have one 2004-06-24 07:36:59 +00:00
SparcRegisterInfo.cpp The long integer pseudo-regs are history. So long, we hardly knew ye. 2004-06-24 08:55:21 +00:00
SparcRegisterInfo.h
SparcRegisterInfo.td Make the double-fp pseudo registers be "NamedRegs". 2004-06-24 09:23:21 +00:00
SparcTargetMachine.cpp Order #includes as per style guide. 2004-06-21 21:54:40 +00:00
SparcTargetMachine.h Adjust to new TM interfaces 2004-06-02 05:47:26 +00:00
SparcV8CodeEmitter.cpp
SparcV8InstrInfo_F2.td
SparcV8InstrInfo_F3.td Clean up the commented-out F3_3 stuff. 2004-06-18 06:28:21 +00:00
SparcV8ISelSimple.cpp Support cast float to float, cast double to float, and cast float to double. 2004-06-24 21:22:08 +00:00
SparcV8JITInfo.h

SparcV8 backend skeleton
------------------------

This directory will house a 32-bit SPARC V8 backend employing a expander-based
instruction selector.  Watch this space for more news coming soon!

$Date$