llvm-6502

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History

Jakob Stoklund Olesen 4a0a18af4a Permit remat of partial register defs when it is safe.

An instruction may define part of a register where the other bits are
undefined. In that case, it is safe to rematerialize the instruction.
For example:

  %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>

The extra <imp-def> operand indicates that the instruction does not read
the other parts of the virtual register, so a remat is safe.

This patch simply allows multiple def operands for the virtual register.
It is MI->readsVirtualRegister() that determines if we depend on a
previous value so remat is impossible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138953 91177308-0d34-0410-b5e6-96231b3b80d8

2011-09-01 18:27:51 +00:00

Analysis

After r138010, subroutine type does not have context info. Update type verifier accordingly.

2011-08-31 18:04:31 +00:00