mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-17 21:35:07 +00:00
2f69e4cf32
There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA).
This assert needs to addressed for post RA scheduler. Until that assert is addressed,
any passes that uses post ra scheduler will fail. So, I am temporarily disabling the
hexagon tests until that fix is in.
The assert is as follows:
assert(!MI->isTerminator() && !MI->isLabel() &&
"Cannot schedule terminators or labels!");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154617 91177308-0d34-0410-b5e6-96231b3b80d8
18 lines
427 B
LLVM
18 lines
427 B
LLVM
; RUN: true
|
|
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
|
|
; CHECK: r[[T0:[0-9]+]] = CONST32(#s2)
|
|
; CHECK: r[[T1:[0-9]+]] = memw(r[[T0]] + #0)
|
|
; CHECK: memw(r29 + #0) = r[[T1]]
|
|
|
|
%struct.large = type { i64, i64 }
|
|
|
|
@s2 = common global %struct.large zeroinitializer, align 8
|
|
|
|
define void @foo() nounwind {
|
|
entry:
|
|
call void @bar(%struct.large* byval @s2)
|
|
ret void
|
|
}
|
|
|
|
declare void @bar(%struct.large* byval)
|